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26 lines
411 B
Verilog
26 lines
411 B
Verilog
`default_nettype none
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module servant_ecp5_clock_gen
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(
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input i_clk,
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input i_rst,
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output o_clk,
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output o_rst);
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wire locked;
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reg [1:0] rst_reg;
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always @(posedge o_clk)
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if (i_rst)
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rst_reg <= 2'b11;
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else
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rst_reg <= {!locked, rst_reg[1]};
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assign o_rst = rst_reg[0];
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pll pll
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(.clki (i_clk),
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.clko (o_clk),
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.locked (locked));
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endmodule
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