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90 lines
2.4 KiB
Verilog
90 lines
2.4 KiB
Verilog
/*
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mem = 00
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gpio = 01
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timer = 10
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testcon = 11
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*/
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module servant_mux
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(
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input wire i_clk,
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input wire i_rst,
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input wire [31:0] i_wb_cpu_adr,
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input wire [31:0] i_wb_cpu_dat,
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input wire [3:0] i_wb_cpu_sel,
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input wire i_wb_cpu_we,
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input wire i_wb_cpu_cyc,
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output wire [31:0] o_wb_cpu_rdt,
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output reg o_wb_cpu_ack,
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output wire [31:0] o_wb_mem_adr,
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output wire [31:0] o_wb_mem_dat,
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output wire [3:0] o_wb_mem_sel,
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output wire o_wb_mem_we,
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output wire o_wb_mem_cyc,
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input wire [31:0] i_wb_mem_rdt,
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output wire o_wb_gpio_dat,
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output wire o_wb_gpio_we,
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output wire o_wb_gpio_cyc,
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input wire i_wb_gpio_rdt,
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output wire [31:0] o_wb_timer_dat,
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output wire o_wb_timer_we,
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output wire o_wb_timer_cyc,
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input wire [31:0] i_wb_timer_rdt);
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parameter sim = 0;
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wire [1:0] s = i_wb_cpu_adr[31:30];
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assign o_wb_cpu_rdt = s[1] ? i_wb_timer_rdt :
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s[0] ? {31'd0,i_wb_gpio_rdt} : i_wb_mem_rdt;
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always @(posedge i_clk) begin
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o_wb_cpu_ack <= 1'b0;
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if (i_wb_cpu_cyc & !o_wb_cpu_ack)
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o_wb_cpu_ack <= 1'b1;
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if (i_rst)
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o_wb_cpu_ack <= 1'b0;
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end
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assign o_wb_mem_adr = i_wb_cpu_adr;
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assign o_wb_mem_dat = i_wb_cpu_dat;
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assign o_wb_mem_sel = i_wb_cpu_sel;
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assign o_wb_mem_we = i_wb_cpu_we;
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assign o_wb_mem_cyc = i_wb_cpu_cyc & (s == 2'b00);
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assign o_wb_gpio_dat = i_wb_cpu_dat[0];
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assign o_wb_gpio_we = i_wb_cpu_we;
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assign o_wb_gpio_cyc = i_wb_cpu_cyc & (s == 2'b01);
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assign o_wb_timer_dat = i_wb_cpu_dat;
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assign o_wb_timer_we = i_wb_cpu_we;
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assign o_wb_timer_cyc = i_wb_cpu_cyc & s[1];
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generate
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if (sim) begin
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wire sig_en = (i_wb_cpu_adr[31:28] == 4'h8) & i_wb_cpu_cyc & o_wb_cpu_ack;
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wire halt_en = (i_wb_cpu_adr[31:28] == 4'h9) & i_wb_cpu_cyc & o_wb_cpu_ack;
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reg [1023:0] signature_file;
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integer f = 0;
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initial
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/* verilator lint_off WIDTH */
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if ($value$plusargs("signature=%s", signature_file)) begin
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$display("Writing signature to %0s", signature_file);
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f = $fopen(signature_file, "w");
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end
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/* verilator lint_on WIDTH */
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always @(posedge i_clk)
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if (sig_en & (f != 0))
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$fwrite(f, "%c", i_wb_cpu_dat[7:0]);
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else if(halt_en) begin
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$display("Test complete");
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$finish;
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end
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end
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endgenerate
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endmodule
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