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https://github.com/olofk/serv.git
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51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
`default_nettype none
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module servclone10_clock_gen
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(input wire i_clk,
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input wire i_rst,
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output wire o_clk,
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output wire o_rst);
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wire [4:0] clk;
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wire clk_fb;
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wire locked;
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reg [9:0] r;
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assign o_clk = clk[0];
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assign o_rst = r[9];
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always @(posedge o_clk)
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if (locked)
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r <= {r[8:0],1'b0};
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else
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r <= 10'b1111111111;
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cyclone10lp_pll
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#(.bandwidth_type ("auto"),
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.clk0_divide_by (6),
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.clk0_duty_cycle (50),
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.clk0_multiply_by (16),
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.clk0_phase_shift ("0"),
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.compensate_clock ("clk0"),
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.inclk0_input_frequency (83333),
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.operation_mode ("normal"),
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.pll_type ("auto"),
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.lpm_type ("cyclone10lp_pll"))
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pll
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(.activeclock (),
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.areset (i_rst),
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.clk (clk),
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.clkbad (),
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.fbin (clk_fb),
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.fbout (clk_fb),
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.inclk (i_clk),
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.locked (locked),
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.phasedone (),
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.scandataout (),
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.scandone (),
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.vcooverrange (),
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.vcounderrange ());
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endmodule
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