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56 lines
1.2 KiB
Verilog
56 lines
1.2 KiB
Verilog
`default_nettype none
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module serv_decode_tb;
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reg clk = 1'b1;
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reg [31:0] i_rd_dat = 32'd0;
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reg i_rd_vld = 1'b0;
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wire i_rd_rdy;
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wire ctrl_en;
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wire ctrl_jump;
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wire [4:0] rd_addr;
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wire [4:0] rs1_addr;
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wire [4:0] rs2_addr;
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wire imm;
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wire offset_source;
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wire [1:0] rd_source;
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reg [31:0] tb_imm;
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always #5 clk <= !clk;
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vlog_tb_utils vtu();
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serv_decode decode
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(
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.clk (clk),
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.i_i_rd_dat (i_rd_dat),
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.i_i_rd_vld (i_rd_vld),
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.o_i_rd_rdy (i_rd_rdy),
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.o_ctrl_en (ctrl_en),
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.o_ctrl_jump (ctrl_jump),
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.o_rf_rd_addr (rd_addr),
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.o_rf_rs1_addr (rs1_addr),
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.o_rf_rs2_addr (rs2_addr),
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.o_imm (imm),
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.o_offset_source (offset_source),
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.o_rd_source (rd_source));
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initial begin
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@(posedge clk);
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i_rd_dat <= 32'h3d80006f;
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i_rd_vld <= 1'b1;
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@(posedge clk);
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@(posedge i_rd_rdy);
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@(posedge clk);
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$display("imm = %08x", tb_imm);
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$finish;
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end
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always @(posedge clk) begin
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if (ctrl_en)
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tb_imm <= {imm, tb_imm[31:1]};
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end
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endmodule
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