mirror of
https://github.com/olofk/serv.git
synced 2026-02-03 23:02:33 +00:00
112 lines
2.6 KiB
Verilog
112 lines
2.6 KiB
Verilog
`default_nettype none
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module serv_top_tb;
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reg clk = 1'b1;
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wire [31:0] i_ca_adr;
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wire i_ca_vld;
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wire i_ca_rdy;
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wire [31:0] i_rd_dat;
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wire i_rd_vld;
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wire i_rd_rdy;
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wire d_ca_cmd;
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wire [31:0] d_ca_adr;
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wire d_ca_vld;
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wire d_ca_rdy;
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wire [31:0] d_dm_dat;
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wire [3:0] d_dm_msk;
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wire d_dm_vld;
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wire d_dm_rdy;
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wire [31:0] d_rd_dat;
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wire d_rd_vld;
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wire d_rd_rdy;
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reg [1023:0] firmware_file;
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reg [31:0] pc;
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reg [31:0] instruction;
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always #5 clk <= !clk;
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camd_ram
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#(.memfile ("firmware.hex"),
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.depth (16384*4))
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i_mem
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(.clk_i (clk),
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.rst_i (1'b0),
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.ca_adr_i (i_ca_adr),
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.ca_cmd_i (1'b0/*i_ca_cmd*/),
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.ca_vld_i (i_ca_vld),
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.ca_rdy_o (i_ca_rdy),
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.dm_dat_i (/*i_dm_dat*/),
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.dm_msk_i (/*i_dm_msk*/),
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.dm_vld_i (/*i_dm_vld*/),
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.dm_rdy_o (/*i_dm_rdy*/),
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.rd_dat_o (i_rd_dat),
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.rd_vld_o (i_rd_vld),
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.rd_rdy_i (i_rd_rdy));
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camd_ram
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#(.memfile ("firmware.hex"),
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.depth (16384*4))
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d_mem
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(.clk_i (clk),
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.rst_i (1'b0),
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.ca_adr_i (d_ca_adr),
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.ca_cmd_i (d_ca_cmd),
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.ca_vld_i (d_ca_vld),
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.ca_rdy_o (d_ca_rdy),
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.dm_dat_i (d_dm_dat),
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.dm_msk_i (d_dm_msk),
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.dm_vld_i (d_dm_vld),
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.dm_rdy_o (d_dm_rdy),
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.rd_dat_o (d_rd_dat),
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.rd_vld_o (d_rd_vld),
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.rd_rdy_i (d_rd_rdy));
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reg catch_write = 1'b0;
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reg dbg = 1'b0;
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wire d_ca_en = d_ca_vld & d_ca_rdy;
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wire d_dm_en = d_dm_vld & d_dm_rdy;
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always @(posedge clk) begin
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dbg <= 1'b0;
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if (d_ca_en & d_ca_cmd & (d_ca_adr == 32'h10000000))
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catch_write <= 1'b1;
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if (((d_ca_en & d_ca_cmd & (d_ca_adr == 32'h10000000)) |catch_write) & d_dm_en & d_dm_msk[0]) begin
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dbg <= 1'b1;
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$write("%c", d_dm_dat[7:0]);
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$fflush();
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catch_write <= 1'b0;
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end
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end
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vlog_tb_utils vtu();
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serv_top
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#(.RESET_PC (32'd8))
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dut
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(
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.clk (clk),
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.o_i_ca_adr (i_ca_adr),
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.o_i_ca_vld (i_ca_vld),
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.i_i_ca_rdy (i_ca_rdy),
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.i_i_rd_dat (i_rd_dat),
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.i_i_rd_vld (i_rd_vld),
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.o_i_rd_rdy (i_rd_rdy),
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.o_d_ca_cmd (d_ca_cmd),
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.o_d_ca_adr (d_ca_adr),
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.o_d_ca_vld (d_ca_vld),
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.i_d_ca_rdy (d_ca_rdy),
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.o_d_dm_dat (d_dm_dat),
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.o_d_dm_msk (d_dm_msk),
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.o_d_dm_vld (d_dm_vld),
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.i_d_dm_rdy (d_dm_rdy),
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.i_d_rd_dat (d_rd_dat),
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.i_d_rd_vld (d_rd_vld),
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.o_d_rd_rdy (d_rd_rdy));
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endmodule
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