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56 lines
1.3 KiB
Verilog
56 lines
1.3 KiB
Verilog
module camd_ram
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#(//camd parameters
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parameter AW = 32,
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parameter DW = 32,
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//Memory parameters
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parameter depth = 256,
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parameter aw = $clog2(depth),
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parameter memfile = "")
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(input clk_i,
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input rst_i,
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input [AW-1:0] ca_adr_i, //FIXME width = AW-clog2(WB_DW/8)
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input ca_cmd_i,
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input ca_vld_i,
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output ca_rdy_o,
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input [DW-1:0] dm_dat_i,
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input [DW/8-1:0] dm_msk_i,
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input dm_vld_i,
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output dm_rdy_o,
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output [DW-1:0] rd_dat_o,
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output reg rd_vld_o,
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input rd_rdy_i);
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wire ca_en = ca_vld_i & ca_rdy_o;
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wire dm_en = dm_vld_i & dm_rdy_o;
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wire ram_we = ca_en & dm_en;
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assign ca_rdy_o = 1'b1;
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assign dm_rdy_o = 1'b1;
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wire [aw-1:2] raddr;
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reg [aw-1:2] latched_raddr;
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assign raddr = ca_en ? ca_adr_i[aw-1:2] : latched_raddr;
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always @(posedge clk_i) begin
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if (ca_en)
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latched_raddr <= ca_adr_i[aw-1:2];
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rd_vld_o <= 1'b0;
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if (ca_en & !ca_cmd_i)
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rd_vld_o <= 1'b1;
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end
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wb_ram_generic
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#(.depth(depth/4),
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.memfile (memfile))
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ram0
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(.clk (clk_i),
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.we ({4{ram_we}} & dm_msk_i),
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.din (dm_dat_i),
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.waddr (ca_adr_i[aw-1:2]),
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.raddr (raddr),
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.dout (rd_dat_o));
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endmodule
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