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20 lines
341 B
Verilog
20 lines
341 B
Verilog
`default_nettype none
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module ser_lt
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(
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input i_clk,
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input i_a,
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input i_b,
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input i_clr,
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output reg o_q);
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reg lt_r = 1'b0;
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wire lt = (~i_a & i_b) | ((i_a == i_b) & lt_r);
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always @(posedge i_clk) begin
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lt_r <= lt & ~i_clr;
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if (~i_clr)
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o_q <= lt;
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end
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endmodule
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