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79 lines
1.5 KiB
Verilog
79 lines
1.5 KiB
Verilog
`default_nettype none
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module ser_add_tb;
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localparam MAX_LEN = 6;
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reg clk = 1'b1;
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reg a = 1'b0;
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reg b = 1'b0;
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wire q;
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reg clear = 1'b0;
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vlog_tb_utils vtu();
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always #5 clk <= !clk;
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initial begin
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@(posedge clk);
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repeat (1000) do_transaction;
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$finish;
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end
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task do_transaction;
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integer len;
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integer idx;
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integer areg, breg;
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integer received, expected;
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beginUsing 0d bits
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len = 0;
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while (len < 1)
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len = ($random % MAX_LEN) + 1;
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areg = $random & ((2**len)-1);
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breg = $random & ((2**len)-1);
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expected = areg+breg;
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received = 0/*'dx*/;
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$write("Using %0d bits. Expecting %0d+%0d=%0d...", len, areg, breg, expected);
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for (idx=0;idx<len;idx=idx+1) begin
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clear <= (idx == 0);
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a <= areg[idx];
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b <= breg[idx];
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@(posedge clk);
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received[idx-1] = q;
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end
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clear <= 1'b0;
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a <= 1'b0;
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b <= 1'b0;
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@(posedge clk);
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received[len-1] = q;
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@(posedge clk);
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received[len] = q;
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if (received == expected)
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$display("OK");
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else begin
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$display("Crap! Got %0d", received);
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#100 $finish;
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end
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@(posedge clk);
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end
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endtask
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ser_add dut
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(
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.clk (clk),
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.a (a),
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.b (b),
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.clear (clear),
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.q (q));
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endmodule
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