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27621a285e
Synopysis DC has problems with forward references and initial statements. Fixed that for better compatibility.
21 lines
428 B
Verilog
21 lines
428 B
Verilog
module shift_reg
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#(parameter LEN = 0,
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parameter INIT = 0)
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(
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input wire clk,
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input wire i_rst,
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input wire i_en,
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input wire i_d,
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output wire o_q,
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output wire [LEN-2:0] o_par);
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reg [LEN-1:0] data;
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assign o_q = data[0];
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assign o_par = data[LEN-1:1];
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always @(posedge clk)
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if (i_rst)
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data <= INIT;
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else if (i_en)
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data <= {i_d, data[LEN-1:1]};
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endmodule
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