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16 lines
213 B
Verilog
16 lines
213 B
Verilog
module ser_add
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(
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input clk,
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input a,
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input b,
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input clr,
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output q);
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reg c = 1'b0;
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assign q = a ^ b ^ c;
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always @(posedge clk)
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c <= !clr & (a&b | a&c | b&c);
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endmodule
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