mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 15:17:25 +00:00
20 lines
277 B
Verilog
20 lines
277 B
Verilog
`default_nettype none
|
|
module ser_eq
|
|
(
|
|
input clk,
|
|
input a,
|
|
input b,
|
|
input clr,
|
|
output reg o_q);
|
|
|
|
reg eq = 1'b1;
|
|
|
|
wire q = eq & (a == b);
|
|
always @(posedge clk) begin
|
|
eq <= q | clr;
|
|
if (!clr)
|
|
o_q <= q;
|
|
end
|
|
|
|
endmodule
|