mirror of
https://github.com/olofk/serv.git
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88 lines
1.7 KiB
Verilog
88 lines
1.7 KiB
Verilog
`default_nettype none
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module serv_alu
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(
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input clk,
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input i_en,
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input [2:0] i_op,
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input [2:0] i_funct3,
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input i_rs1,
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input i_op_b,
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input i_init,
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output o_cmp,
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input i_shamt_en,
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output o_rd);
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`include "serv_params.vh"
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localparam[2:0]
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BEQ = 3'b000,
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BNE = 3'b001;
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wire result_add;
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wire result_eq;
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wire result_sh;
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wire [4:0] shamt;
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reg en_r;
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shift_reg #(.LEN (5)) shamt_reg
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(.clk (clk),
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.i_en (i_shamt_en),
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.i_d (i_op_b),
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.o_q (shamt[0]),
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.o_par (shamt[4:1]));
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ser_shift shift
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(
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.i_clk (clk),
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.i_load (i_init),
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.i_shamt (shamt),
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.i_sr (/*FIXME*/),
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.i_d (i_rs1),
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.o_q (result_sh));
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wire plus_1 = i_en & !en_r;
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wire b_inv_plus_1;
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ser_add ser_add_inv_plus_1
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(
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.clk (clk),
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.a (~i_op_b),
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.b (plus_1),
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.clr (!i_en),
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.q (b_inv_plus_1));
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wire add_b = sub ? b_inv_plus_1 : i_op_b;
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wire sub = i_op[1];
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ser_add ser_add
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(
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.clk (clk),
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.a (i_rs1),
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.b (add_b),
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.clr (!i_en),
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.q (result_add));
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ser_eq ser_eq
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(
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.clk (clk),
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.a (i_rs1),
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.b (i_op_b),
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.clr (!i_init),
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.o_q (result_eq));
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assign o_cmp = (i_funct3 == BEQ) ? result_eq :
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(i_funct3 == BNE) ? ~result_eq : 1'bx;
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assign o_rd = (i_op == ALU_OP_ADD) ? result_add :
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(i_op == ALU_OP_SUB) ? result_add :
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(i_op == ALU_OP_SR) ? result_sh :
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1'bx;
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always @(posedge clk)
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en_r <= i_en;
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endmodule
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