mirror of
https://github.com/olofk/serv.git
synced 2026-01-13 15:17:25 +00:00
144 lines
3.3 KiB
Verilog
144 lines
3.3 KiB
Verilog
`default_nettype none
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module serv_regfile
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(
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input i_clk,
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input i_rd_en,
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input [4:0] i_rd_addr,
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input i_rd,
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input [4:0] i_rs1_addr,
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input [4:0] i_rs2_addr,
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input i_rs_en,
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output o_rs1,
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output o_rs2);
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//reg [31:0] rf [0:31];
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`ifndef SYNTHESIS
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/* always @(*)
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for (i=0;i<32;i=i+1) begin
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dbg_x1[i] = rf[i][1];
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dbg_x2[i] = rf[i][2];
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dbg_x3[i] = rf[i][3];
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dbg_x4[i] = rf[i][4];
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dbg_x5[i] = rf[i][5];
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dbg_x6[i] = rf[i][6];
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dbg_x7[i] = rf[i][7];
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dbg_x8[i] = rf[i][8];
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dbg_x9[i] = rf[i][9];
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dbg_x10[i] = rf[i][10];
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dbg_x11[i] = rf[i][11];
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dbg_x12[i] = rf[i][12];
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dbg_x13[i] = rf[i][13];
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dbg_x14[i] = rf[i][14];
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dbg_x15[i] = rf[i][15];
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dbg_x16[i] = rf[i][16];
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dbg_x17[i] = rf[i][17];
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dbg_x18[i] = rf[i][18];
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dbg_x19[i] = rf[i][19];
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dbg_x20[i] = rf[i][20];
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dbg_x21[i] = rf[i][21];
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dbg_x22[i] = rf[i][22];
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dbg_x23[i] = rf[i][23];
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dbg_x24[i] = rf[i][24];
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dbg_x25[i] = rf[i][25];
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dbg_x26[i] = rf[i][26];
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dbg_x27[i] = rf[i][27];
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dbg_x28[i] = rf[i][28];
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dbg_x29[i] = rf[i][29];
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dbg_x30[i] = rf[i][30];
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dbg_x31[i] = rf[i][31];
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end
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*/
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reg [31:0] dbg_x0 ;
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reg [31:0] dbg_x1 ;
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reg [31:0] dbg_x2 ;
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reg [31:0] dbg_x3 ;
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reg [31:0] dbg_x4 ;
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reg [31:0] dbg_x5 ;
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reg [31:0] dbg_x6 ;
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reg [31:0] dbg_x7 ;
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reg [31:0] dbg_x8 ;
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reg [31:0] dbg_x9 ;
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reg [31:0] dbg_x10;
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reg [31:0] dbg_x11;
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reg [31:0] dbg_x12;
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reg [31:0] dbg_x13;
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reg [31:0] dbg_x14;
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reg [31:0] dbg_x15;
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reg [31:0] dbg_x16;
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reg [31:0] dbg_x17;
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reg [31:0] dbg_x18;
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reg [31:0] dbg_x19;
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reg [31:0] dbg_x20;
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reg [31:0] dbg_x21;
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reg [31:0] dbg_x22;
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reg [31:0] dbg_x23;
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reg [31:0] dbg_x24;
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reg [31:0] dbg_x25;
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reg [31:0] dbg_x26;
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reg [31:0] dbg_x27;
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reg [31:0] dbg_x28;
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reg [31:0] dbg_x29;
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reg [31:0] dbg_x30;
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reg [31:0] dbg_x31;
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integer i;
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// initial for (i=0; i<32; i=i+1) rf[i] = 0;
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`endif
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reg [4:0] raddr = 5'd1;
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reg [4:0] waddr = 5'd0;
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// reg [31:0] rs = 32'd0;
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wire [31:0] rs;
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reg [31:0] mask;
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always @(i_rd_addr)
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mask = ~(1 << i_rd_addr);
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SB_RAM40_4K rf0
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(
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.RDATA (rs[15:0]),
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.RCLK (i_clk),
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.RCLKE (1'b1),
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.RE (1'b1),
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.RADDR ({6'd0,raddr2}),
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.WCLK (i_clk),
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.WCLKE (1'b1),
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.WE (i_rd_en),
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.WADDR ({6'd0,waddr}),
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.MASK (mask[15:0]),
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.WDATA ({16{i_rd}})
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);
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SB_RAM40_4K rf1
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(
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.RDATA (rs[31:16]),
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.RCLK (i_clk),
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.RCLKE (1'b1),
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.RE (1'b1),
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.RADDR ({6'd0,raddr2}),
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.WCLK (i_clk),
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.WCLKE (1'b1),
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.WE (i_rd_en),
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.WADDR ({6'd0,waddr}),
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.MASK (mask[31:16]),
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.WDATA ({16{i_rd}})
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);
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always @(posedge i_clk) begin
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if (i_rd_en) begin
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waddr <= waddr + 1;
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//rf[waddr][i_rd_addr] <= i_rd;
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end
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if (i_rs_en)
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raddr <= raddr + 1;
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//rs <= rf[raddr2];
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end
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wire [4:0] raddr2 = raddr & {5{i_rs_en}};
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assign o_rs1 = (|i_rs1_addr) ? rs[i_rs1_addr] : 1'b0;
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assign o_rs2 = (|i_rs2_addr) ? rs[i_rs2_addr] : 1'b0;
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endmodule
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