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69 lines
1.4 KiB
Verilog
69 lines
1.4 KiB
Verilog
module serv_decode
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(
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input clk,
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input i_go,
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input i_instr,
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output o_imm_31_12,
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output o_imm_11_0,
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output o_rd,
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output o_field_rs2,
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output o_field_rs1,
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output o_funct3,
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output o_funct7,
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output o_jal,
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output o_opimm,
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output o_alu_go,
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output o_ctrl_go);
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localparam [4:0]
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OP_OPIMM = 5'b00100,
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OP_JAL = 5'b11011;
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reg [8:0] barrel [0:31];
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reg [4:0] cnt = 5'd0;
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reg running = 1'b0;
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wire opcode_valid;
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wire halt;
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wire [8:0] cur = barrel[cnt];
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assign o_imm_31_12 = cur[8];
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assign o_imm_11_0 = cur[7];
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assign o_rd = cur[6];
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assign o_field_rs2 = cur[5] & (1'b0);
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assign o_field_rs1 = cur[4] & (1'b0);
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assign o_funct3 = cur[3];
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assign o_funct7 = cur[2];
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assign opcode_valid = cur[1];
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assign halt = cur[0];
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initial begin
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$readmemb("decode.mem", barrel);
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end
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reg [4:0] opcode = 5'd0;
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assign o_jal = (opcode == OP_JAL);
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assign o_ctrl_go = (cnt == 19);
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assign o_opimm = (opcode == OP_OPIMM);
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assign o_alu_go = o_opimm & (cnt == 19);
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// shift_reg #(5) shift_reg_opcode
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always @(posedge clk) begin
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if (opcode_valid)
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opcode <= {opcode[3:0], i_instr};
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cnt <= cnt + (i_go | running);
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if (i_go)
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running <= 1'd1;
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else if (halt) begin
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running <= 1'd0;
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cnt <= 1'b0;
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end
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end
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endmodule
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