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43 lines
896 B
Verilog
43 lines
896 B
Verilog
`default_nettype none
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module ser_shift
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(
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input wire i_clk,
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input wire i_load,
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input wire [4:0] i_shamt,
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input wire i_signed,
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input wire i_right,
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input wire i_d,
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output wire o_q);
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wire [31:0] shiftreg;
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reg signbit = 1'b0;
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reg wrapped = 1'b0;
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reg [4:0] cnt = 5'd0;
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shift_reg #(.LEN (32)) sh_reg
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(.clk (i_clk),
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.i_en (i_load),
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.i_d (i_d),
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.o_q (shiftreg[0]),
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.o_par (shiftreg[31:1]));
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always @(posedge i_clk) begin
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cnt <= cnt + 1;
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if (cnt == 31) begin
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signbit <= shiftreg[cnt];
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wrapped <= 1'b1;
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end
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if (i_load) begin
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cnt <= i_shamt;
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wrapped <= 1'b0;
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end
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end
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wire shiftreg_valid = (i_shamt == 0) | (wrapped^i_right);
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assign o_q = shiftreg_valid ? shiftreg[cnt] : signbit & i_signed;
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endmodule
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