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31 lines
802 B
Verilog
31 lines
802 B
Verilog
`default_nettype none
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module servax_clock_gen
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(input wire i_clk,
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output wire o_clk,
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output reg o_rst);
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wire locked;
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reg locked_r;
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DCM_SP #(
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.CLKFX_DIVIDE(25), // Can be any integer from 1 to 32
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.CLKFX_MULTIPLY(8), // Can be any integer from 2 to 32
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.CLKIN_PERIOD(20.0) //50Mhz
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)
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DCM_SP_inst (
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.CLKFX(o_clk), // DCM CLK synthesis out (M/D)
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.CLKFX180(), // 180 degree CLK synthesis out
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.LOCKED(locked), // DCM LOCK status output
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.STATUS(), // 8-bit DCM status bits output
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.CLKFB(), // DCM clock feedback
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.CLKIN(i_clk), // Clock input
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.RST(1'b0) // DCM asynchronous reset input
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);
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always @(posedge o_clk) begin
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locked_r <= locked;
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o_rst <= !locked_r;
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end
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endmodule |