mirror of
https://github.com/olofk/serv.git
synced 2026-01-15 15:56:04 +00:00
40000cbeb9
This contains a lot of fixes as IRQ support was broken on both RTL and zephyr side * Interrupts are now synced to instruction lifetimes * Interrupts are disabled on traps and mie is pushed to mpie * Zephyr applications regenerated from rewritten Zephyr port * Timer is 32-bit to avoid wrapping around too often * MEPC was not read properly from CSR storage
202 lines
4.9 KiB
Verilog
202 lines
4.9 KiB
Verilog
`default_nettype none
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module servant
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(
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input wire wb_clk,
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input wire wb_rst,
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output wire q);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire timer_irq;
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wire [31:0] wb_cpu_ibus_adr;
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wire wb_cpu_ibus_cyc;
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wire [31:0] wb_cpu_ibus_rdt;
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wire wb_cpu_ibus_ack;
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wire [31:0] wb_cpu_dbus_adr;
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wire [31:0] wb_cpu_dbus_dat;
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wire [3:0] wb_cpu_dbus_sel;
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wire wb_cpu_dbus_we;
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wire wb_cpu_dbus_cyc;
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wire [31:0] wb_cpu_dbus_rdt;
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wire wb_cpu_dbus_ack;
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wire [31:0] wb_dmux_mem_adr;
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wire [31:0] wb_dmux_mem_dat;
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wire [3:0] wb_dmux_mem_sel;
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wire wb_dmux_mem_we;
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wire wb_dmux_mem_cyc;
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wire [31:0] wb_dmux_mem_rdt;
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wire wb_dmux_mem_ack;
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wire [31:0] wb_mem_adr;
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wire [31:0] wb_mem_dat;
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wire [3:0] wb_mem_sel;
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wire wb_mem_we;
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wire wb_mem_cyc;
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wire [31:0] wb_mem_rdt;
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wire wb_mem_ack;
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wire wb_gpio_dat;
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wire wb_gpio_we;
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wire wb_gpio_cyc;
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wire wb_gpio_rdt;
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wire [31:0] wb_timer_dat;
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wire wb_timer_we;
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wire wb_timer_cyc;
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wire [31:0] wb_timer_rdt;
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servant_arbiter servant_arbiter
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(
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.i_wb_cpu_dbus_adr (wb_dmux_mem_adr),
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.i_wb_cpu_dbus_dat (wb_dmux_mem_dat),
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.i_wb_cpu_dbus_sel (wb_dmux_mem_sel),
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.i_wb_cpu_dbus_we (wb_dmux_mem_we ),
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.i_wb_cpu_dbus_cyc (wb_dmux_mem_cyc),
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.o_wb_cpu_dbus_rdt (wb_dmux_mem_rdt),
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.o_wb_cpu_dbus_ack (wb_dmux_mem_ack),
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.i_wb_cpu_ibus_adr (wb_cpu_ibus_adr),
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.i_wb_cpu_ibus_cyc (wb_cpu_ibus_cyc),
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.o_wb_cpu_ibus_rdt (wb_cpu_ibus_rdt),
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.o_wb_cpu_ibus_ack (wb_cpu_ibus_ack),
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.o_wb_cpu_adr (wb_mem_adr),
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.o_wb_cpu_dat (wb_mem_dat),
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.o_wb_cpu_sel (wb_mem_sel),
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.o_wb_cpu_we (wb_mem_we ),
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.o_wb_cpu_cyc (wb_mem_cyc),
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.i_wb_cpu_rdt (wb_mem_rdt),
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.i_wb_cpu_ack (wb_mem_ack));
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`ifdef VERILATOR
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parameter sim = 1;
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`else
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parameter sim = 0;
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`endif
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servant_mux #(sim) servant_mux
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(
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.i_clk (wb_clk),
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.i_rst (wb_rst),
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.i_wb_cpu_adr (wb_cpu_dbus_adr),
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.i_wb_cpu_dat (wb_cpu_dbus_dat),
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.i_wb_cpu_sel (wb_cpu_dbus_sel),
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.i_wb_cpu_we (wb_cpu_dbus_we),
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.i_wb_cpu_cyc (wb_cpu_dbus_cyc),
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.o_wb_cpu_rdt (wb_cpu_dbus_rdt),
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.o_wb_cpu_ack (wb_cpu_dbus_ack),
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.o_wb_mem_adr (wb_dmux_mem_adr),
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.o_wb_mem_dat (wb_dmux_mem_dat),
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.o_wb_mem_sel (wb_dmux_mem_sel),
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.o_wb_mem_we (wb_dmux_mem_we),
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.o_wb_mem_cyc (wb_dmux_mem_cyc),
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.i_wb_mem_rdt (wb_dmux_mem_rdt),
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.o_wb_gpio_dat (wb_gpio_dat),
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.o_wb_gpio_we (wb_gpio_we),
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.o_wb_gpio_cyc (wb_gpio_cyc),
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.i_wb_gpio_rdt (wb_gpio_rdt),
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.o_wb_timer_dat (wb_timer_dat),
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.o_wb_timer_we (wb_timer_we),
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.o_wb_timer_cyc (wb_timer_cyc),
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.i_wb_timer_rdt (wb_timer_rdt));
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`ifndef SYNTHESIS
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//synthesis translate_off
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reg [1023:0] firmware_file;
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initial
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/* verilator lint_off WIDTH */
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if ($value$plusargs("firmware=%s", firmware_file)) begin
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$display("Loading RAM from %0s", firmware_file);
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$readmemh(firmware_file, ram.mem);
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end
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/* verilator lint_on WIDTH */
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//synthesis translate_on
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`endif
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servant_ram
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#(
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`ifndef VERILATOR
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.memfile (memfile),
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`endif
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.depth (memsize))
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ram
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(// Wishbone interface
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.i_wb_clk (wb_clk),
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.i_wb_adr (wb_mem_adr[$clog2(memsize)-1:0]),
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.i_wb_cyc (wb_mem_cyc),
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.i_wb_we (wb_mem_we) ,
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.i_wb_sel (wb_mem_sel),
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.i_wb_dat (wb_mem_dat),
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.o_wb_rdt (wb_mem_rdt),
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.o_wb_ack (wb_mem_ack));
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servant_timer
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#(.WIDTH (32))
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timer
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(.i_clk (wb_clk),
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.i_rst (wb_rst),
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.o_irq (timer_irq),
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.i_wb_cyc (wb_timer_cyc),
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.i_wb_we (wb_timer_we) ,
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.i_wb_dat (wb_timer_dat),
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.o_wb_dat (wb_timer_rdt));
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servant_gpio gpio
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(.i_wb_clk (wb_clk),
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.i_wb_dat (wb_gpio_dat),
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.i_wb_we (wb_gpio_we),
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.i_wb_cyc (wb_gpio_cyc),
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.o_wb_rdt (wb_gpio_rdt),
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.o_gpio (q));
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serv_top
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#(.RESET_PC (32'h0000_0000))
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cpu
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(
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.clk (wb_clk),
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.i_rst (wb_rst),
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.i_timer_irq (timer_irq),
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`ifdef RISCV_FORMAL
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.rvfi_valid (),
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.rvfi_order (),
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.rvfi_insn (),
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.rvfi_trap (),
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.rvfi_halt (),
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.rvfi_intr (),
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.rvfi_mode (),
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.rvfi_ixl (),
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.rvfi_rs1_addr (),
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.rvfi_rs2_addr (),
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.rvfi_rs1_rdata (),
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.rvfi_rs2_rdata (),
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.rvfi_rd_addr (),
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.rvfi_rd_wdata (),
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.rvfi_pc_rdata (),
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.rvfi_pc_wdata (),
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.rvfi_mem_addr (),
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.rvfi_mem_rmask (),
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.rvfi_mem_wmask (),
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.rvfi_mem_rdata (),
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.rvfi_mem_wdata (),
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`endif
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.o_ibus_adr (wb_cpu_ibus_adr),
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.o_ibus_cyc (wb_cpu_ibus_cyc),
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.i_ibus_rdt (wb_cpu_ibus_rdt),
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.i_ibus_ack (wb_cpu_ibus_ack),
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.o_dbus_adr (wb_cpu_dbus_adr),
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.o_dbus_dat (wb_cpu_dbus_dat),
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.o_dbus_sel (wb_cpu_dbus_sel),
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.o_dbus_we (wb_cpu_dbus_we),
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.o_dbus_cyc (wb_cpu_dbus_cyc),
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.i_dbus_rdt (wb_cpu_dbus_rdt),
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.i_dbus_ack (wb_cpu_dbus_ack));
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endmodule
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