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26 lines
591 B
Verilog
26 lines
591 B
Verilog
module serv_rf_ram
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#(parameter width=0,
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parameter depth=32*36/width)
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(input wire i_clk,
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input wire [$clog2(depth)-1:0] i_waddr,
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input wire [width-1:0] i_wdata,
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input wire i_wen,
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input wire [$clog2(depth)-1:0] i_raddr,
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output reg [width-1:0] o_rdata);
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reg [width-1:0] memory [0:depth-1];
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always @(posedge i_clk) begin
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if (i_wen)
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memory[i_waddr] <= i_wdata;
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o_rdata <= memory[i_raddr];
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end
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`ifdef SERV_CLEAR_RAM
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integer i;
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initial
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for (i=0;i<depth;i=i+1)
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memory[i] = {width{1'd0}};
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`endif
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endmodule
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