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32 lines
561 B
Verilog
32 lines
561 B
Verilog
`default_nettype none
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module servclone10
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(
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input wire i_clk,
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input wire i_rst,
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output wire q,
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output wire uart_txd);
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parameter memfile = "zephyr_hello.hex";
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parameter memsize = 8192;
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wire wb_clk;
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wire wb_rst;
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assign uart_txd = q;
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servclone10_clock_gen clock_gen
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(.i_clk (i_clk),
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.i_rst (i_rst),
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.o_clk (wb_clk),
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.o_rst (wb_rst));
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servant
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#(.memfile (memfile),
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.memsize (memsize))
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servant
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(.wb_clk (wb_clk),
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.wb_rst (wb_rst),
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.q (q));
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endmodule
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