mirror of
https://github.com/olofk/serv.git
synced 2026-01-24 11:01:33 +00:00
94 lines
2.1 KiB
Verilog
94 lines
2.1 KiB
Verilog
`default_nettype none
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module serv_alu
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(
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input wire clk,
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input wire i_en,
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input wire i_shift_op,
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input wire i_cnt0,
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input wire i_rs1,
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input wire i_rs2,
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input wire i_imm,
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input wire i_op_b_rs2,
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input wire i_buf,
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input wire i_init,
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input wire i_cnt_done,
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input wire i_sub,
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input wire [1:0] i_bool_op,
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input wire i_cmp_eq,
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input wire i_cmp_sig,
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output wire o_cmp,
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input wire i_shamt_en,
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input wire i_sh_right,
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input wire i_sh_signed,
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output wire o_sh_done,
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input wire [3:0] i_rd_sel,
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output wire o_rd);
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wire result_add;
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wire result_eq;
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wire result_sh;
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reg result_lt_r;
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reg [4:0] shamt;
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reg shamt_msb;
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wire add_cy;
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reg add_cy_r;
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wire op_b = i_op_b_rs2 ? i_rs2 : i_imm;
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serv_shift shift
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(
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.i_clk (clk),
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.i_load (i_init),
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.i_shamt (shamt),
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.i_shamt_msb (shamt_msb),
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.i_signbit (i_sh_signed & i_rs1),
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.i_right (i_sh_right),
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.o_done (o_sh_done),
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.i_d (i_buf),
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.o_q (result_sh));
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//Sign-extended operands
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wire rs1_sx = i_rs1 & i_cmp_sig;
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wire op_b_sx = op_b & i_cmp_sig;
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wire result_lt = rs1_sx + ~op_b_sx + add_cy;
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wire add_a = i_rs1 & ~i_shift_op;
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wire add_b = op_b^i_sub;
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assign {add_cy,result_add} = add_a+add_b+add_cy_r;
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reg eq_r;
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assign result_eq = !result_add & eq_r;
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assign o_cmp = i_cmp_eq ? result_eq : result_lt;
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localparam [15:0] BOOL_LUT = 16'h8E96;//And, Or, =, xor
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wire result_bool = BOOL_LUT[{i_bool_op, i_rs1, op_b}];
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assign o_rd = (i_rd_sel[0] & result_add) |
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(i_rd_sel[1] & result_sh) |
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(i_rd_sel[2] & result_lt_r & i_cnt0) |
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(i_rd_sel[3] & result_bool);
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always @(posedge clk) begin
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add_cy_r <= i_en ? add_cy : i_sub;
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if (i_en) begin
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result_lt_r <= result_lt;
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end
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eq_r <= result_eq | ~i_en;
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if (i_shamt_en) begin
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shamt_msb <= add_cy;
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shamt <= {result_add,shamt[4:1]};
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end
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end
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endmodule
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