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20 lines
290 B
Verilog
20 lines
290 B
Verilog
`default_nettype none
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module ser_eq
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(
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input wire clk,
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input wire a,
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input wire b,
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input wire clr,
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output reg o_q);
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reg eq = 1'b1;
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wire q = eq & (a == b);
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always @(posedge clk) begin
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eq <= q | clr;
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if (!clr)
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o_q <= q;
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end
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endmodule
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