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117 lines
3.9 KiB
ReStructuredText
117 lines
3.9 KiB
ReStructuredText
.. SERV documentation master file, created by
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sphinx-quickstart on Mon Feb 24 00:01:33 2020.
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You can adapt this file completely to your liking, but it should at least
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contain the root `toctree` directive.
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SERV user manual
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================================
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.. toctree::
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:maxdepth: 2
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:caption: Contents:
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Indices and tables
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==================
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* :ref:`genindex`
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* :ref:`modindex`
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* :ref:`search`
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Modules
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-------
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SERV is a bit-serial CPU which means that the internal datapath is one bit wide. :ref:`dataflow` show the internal dataflow. For each instructions, data is read from the register file or the immediate fields of the instruction word and the result of the operation is stored back into the register file. Reading and writing memory is handled through the memory interface module.
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.. _dataflow:
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.. figure:: serv_dataflow.png
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SERV internal dataflow
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serv_rf_top
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^^^^^^^^^^^
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.. image:: serv_rf_top.png
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serv_rf_top is a top-level convenience wrapper that includes SERV and the default RF implementation and just exposes the timer IRQ and instruction/data wishbone buses.
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serv_top
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^^^^^^^^
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serv_top is the top-level of the SERV core without an RF
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serv_alu
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^^^^^^^^
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.. image:: serv_alu.png
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serv_alu handles alu and shift operations. For shift ops, the data to be shifted resides in bufreg. It also contains the logic for comparisons used by the slt* and conditional branch instructions
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.. image:: serv_alu_int.png
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serv_bufreg
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^^^^^^^^^^^
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.. image:: serv_bufreg.png
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For two-stage operations, serv_bufreg holds data between stages. This data can be the effective address for branches or load/stores or data to be shifted for shift ops. It has a serial output for streaming out results during stage two and a parallel output that forms the dbus address. serv_bufreg also keeps track of the two lsb when calculating adresses. This is used to check for alignment errors
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serv_csr
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^^^^^^^^
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.. image:: serv_csr.png
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serv_csr handles CSR accesses and all status related to (timer) interrupts. Out of the eight CSRs supported by SERV, only four resides in serv_csr (mstatus, mie, mcause and mip) and for those registers, SERV only implement the bits required for ecall, ebreak, misalignment and timer interrupts. The four remaining CSRs are commonly stored in the RF
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serv_ctrl
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^^^^^^^^^
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.. image:: serv_ctrl.png
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serv_ctrl keeps track of the current PC and contains the logic needed to calculate the next PC.
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serv_decode
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^^^^^^^^^^^
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.. image:: serv_decode.png
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serv_decode is responsible for decoding the operation word coming from ibus into a set of control signals that are used internally in SERV. It also assembles the 32-bit immediate used by some instructions. During the life cycle of an operation all control signals (except one) are static and the immediate is streamed out during the first run stage
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serv_mem_if
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^^^^^^^^^^^
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.. image:: serv_mem_if.png
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serv_mem_if prepares the data to be sent out on the dbus during store operations and serializes the incoming data during loads
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serv_rf_if
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^^^^^^^^^^
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serv_rf_if is the gateway between the core and an RF implementation. It transforms all control signals that affect register reads or writes and exposes two read and write ports to the RF. This allows implementors to plug in an RF implementation that is best suited for the technology to be used.
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serv_rf_ram
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^^^^^^^^^^^
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serv_rf_ram is the default RF implementation using an SRAM-like interface. Suitable for FPGA implementations
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serv_rf_ram_if
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^^^^^^^^^^^^^^
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serv_rf_ram_if converts between the SERV RF IF and the serv_rf_ram interface
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serv_state
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^^^^^^^^^^
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serv_state keeps track of the state for the core and contains all dynamic control signals during an operations life time. Also controls the accesses towards the RF and dbus
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shift_reg
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^^^^^^^^^
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shift_reg is a shift register implementation used in various places in SERV
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serv_shift
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^^^^^^^^^^
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serv_shift lives inside the ALU and contains the control logic for shift operations
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