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PDP-10 update
Implement keep-alive and os-requested reload functions of FE. Preserve HW config flags during (re-) boot. Allow IPL30 device to interrupt. Add 18-bit DMA functions. Implement DMA to/from I/O space. Optimize DMA memory mapping - once per page, not once per byte. Teach SHOW IO to report vectors and BR levels as well as CSR addresses. Add DUP and KDP to Autoconfigure table.
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@@ -151,6 +151,10 @@ typedef struct {
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d10 ac;
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} InstHistory;
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extern a10 fe_xct; /* Front-end forced XCT */
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extern DEVICE pag_dev;
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extern t_stat pag_reset (DEVICE *dptr);
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d10 *M = NULL; /* memory */
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d10 acs[AC_NBLK * AC_NUM] = { 0 }; /* AC blocks */
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d10 *ac_cur, *ac_prv; /* AC cur, prv (dyn) */
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@@ -708,19 +712,45 @@ xct_cnt = 0; /* count XCT's */
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if (sim_interval <= 0) { /* check clock queue */
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if ((i = sim_process_event ())) /* error? stop sim */
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ABORT (i);
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pi_eval (); /* eval pi system */
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if (fe_xct)
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qintr = -1;
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else
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pi_eval (); /* eval pi system */
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}
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/* PI interrupt (Unibus or system flags).
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On the KS10, only JSR and XPCW are allowed as interrupt instructions.
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Because of exec mode addressing, and unconditional processing of flags,
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they are explicitly emulated here.
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On a keep-alive failure, the console (fe) forces the CPU 'XCT' the
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instruction at exec 71. This is close enough to an interrupt that it is
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treated as one here. TOPS-10 and TOPS-20 use JSR or XPCW, which are
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really the only sensible instructions, as diagnosing a KAF requires the
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PC/FLAGS of the fault.
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On a reload-request from the OS, the fe loads the bootstrap code and sets
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saved_PC. Here, the CPU is partially reset and redirected. (Preserving
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PC history, among other things.) The FE has already reset IO.
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*/
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if (qintr) {
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int32 vec, uba;
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pager_pi = TRUE; /* flag in pi seq */
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if ((vec = pi_ub_vec (qintr, &uba))) { /* Unibus interrupt? */
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if (fe_xct) { /* Console forced execute? */
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qintr = 0;
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if (fe_xct == 1) { /* Forced reload */
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PC = saved_PC; /* Bootstrap PC */
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pager_pi = FALSE;
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ebr = ubr = 0; /* Exec mode, paging & PI off */
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pag_reset (&pag_dev);
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pi_on = pi_enb = pi_act= pi_prq =
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apr_enb = apr_flg = apr_lvl = its_1pr = 0;
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rlog = 0;
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set_newflags (0, FALSE);
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fe_xct = 0;
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continue;
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}
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inst = ReadE(fe_xct); /* Exec address of instruction */
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} else if ((vec = pi_ub_vec (qintr, &uba))) { /* Unibus interrupt? */
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mb = ReadP (epta + EPT_UBIT + uba); /* get dispatch table */
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if (mb == 0) /* invalid? stop */
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ABORT (STOP_ZERINT);
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@@ -750,9 +780,16 @@ if (qintr) {
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JUMP (rs[1]); /* set new PC */
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set_newflags (rs[0], FALSE); /* set new flags */
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}
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else ABORT (STOP_ILLINT); /* invalid instr */
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pi_act = pi_act | pi_l2bit[qintr]; /* set level active */
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pi_eval (); /* eval pi system */
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else {
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fe_xct = 0;
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ABORT (STOP_ILLINT); /* invalid instr */
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}
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if (fe_xct)
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fe_xct = 0;
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else {
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pi_act = pi_act | pi_l2bit[qintr]; /* set level active */
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pi_eval (); /* eval pi system */
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}
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pager_pi = FALSE; /* end of sequence */
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if (sim_interval) /* charge for instr */
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sim_interval--;
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