github.com/open-simh.simh
1
0
Fork 0
mirror of https://github.com/open-simh/simh.git synced 2026-04-30 05:35:22 +00:00
Code Issues Projects Releases Wiki Activity

Merge branch 'open-simh:master' into rp11

Browse Source
This commit is contained in:
Anthony Lawrence
2023-09-22 18:57:51 -04:00
committed by GitHub
parent a653bbfcec d4f85d01bd
commit 14ac68f741
65 changed files with 651 additions and 667 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
PDP11/pdp11_rk.c
View File

@@ -105,9 +105,9 @@
#define RK_NUMTR (RK_NUMCY * RK_NUMSF) /* tracks/drive */
#define RK_NUMDR 8 /* drives/controller */
#define RK_M_NUMDR 07
#define RK_SIZE (RK_NUMCY * RK_NUMSF * RK_NUMSC * RK_NUMWD)
#define RK_NUMBL (RK_NUMTR * RK_NUMSC)
#define RK_SIZE (RK_NUMBL * RK_NUMWD) /* words/drive */
#define RK_RSRVSEC (3 * RK_NUMSF * RK_NUMSC) /* reserved (unused) disk area */
/* words/drive */
#define RK_CTLI 1 /* controller int */
#define RK_SCPI(x) (2u << (x)) /* drive int */
#define RK_MAXFR (1 << 16) /* max transfer */
@@ -122,7 +122,7 @@ struct drvtyp {
};
static struct drvtyp drv_tab[] = {
{ RK_NUMSC, RK_NUMSF, RK_NUMCY, RK_SIZE, "RK05" },
{ RK_NUMSC, RK_NUMSF, RK_NUMCY, RK_NUMBL, "RK05" },
{ 0 }
};
@@ -294,7 +294,7 @@ BITFIELD *rk_reg_bits[] = {
rk_ba_bits,
rk_da_bits,
NULL,
NULL,
NULL
};
/* Debug detail levels */
@@ -324,6 +324,7 @@ int32 last_drv = 0; /* last r/w drive */
int32 rk_stopioe = 1; /* stop on error */
int32 rk_swait = 10; /* seek time */
int32 rk_rwait = 10; /* rotate time */
static int32 not_impl = 0; /* placeholder for unused regs */
const char *rk_regnames[] = {
"RKDS",
@@ -333,7 +334,7 @@ const char *rk_regnames[] = {
"RKBA",
"RKDA",
"unused",
"RKDB",
"RKDB"
};
int32 *rk_regs[] = {
@@ -343,6 +344,8 @@ int32 *rk_regs[] = {
&rkwc,
&rkba,
&rkda,
&not_impl,
&not_impl
};
t_stat rk_rd (int32 *data, int32 PA, int32 access);
@@ -607,7 +610,7 @@ if (func == RKCS_CTLRESET) { /* control reset? */
rker = rker & ~RKER_SOFT; /* clear soft errors */
if (rker == 0) /* redo summary */
rkcs = rkcs & ~RKCS_ERR;
rkcs = rkcs & ~RKCS_SCP; /* clear sch compl*/
rkcs = rkcs & ~RKCS_SCP; /* clear sch compl */
rk_clr_done (); /* clear done */
last_drv = GET_DRIVE (rkda); /* get drive no */
uptr = rk_dev.units + last_drv; /* select unit */
@@ -750,7 +753,7 @@ if (wc && (err == 0)) { /* seek ok? */
else { /* normal store */
if ((t = MAP_WRW (ma, wc << 1, rkxb))) { /* store buf */
rker = rker | RKER_NXM; /* NXM? set flag */
wc = wc - t; /* adj wd cnt */
wc = wc - (t >> 1); /* adj wd cnt */
}
}
break; /* end read */
@@ -765,16 +768,16 @@ if (wc && (err == 0)) { /* seek ok? */
rkxb[i] = comp;
}
else { /* normal fetch */
if ((t = MAP_RDW (ma, wc << 1, rkxb))) { /* get buf */
if ((t = MAP_RDW (ma, wc << 1, rkxb))) { /* get buf */
rker = rker | RKER_NXM; /* NXM? set flg */
wc = wc - t; /* adj wd cnt */
wc = wc - (t >> 1); /* adj wd cnt */
}
}
if (wc) { /* any xfer? */
awc = (wc + (RK_NUMWD - 1)) & ~(RK_NUMWD - 1); /* clr to */
for (i = wc; i < awc; i++) /* end of blk */
rkxb[i] = 0;
sim_disk_data_trace (uptr, (uint8 *)rkxb, da/RK_NUMWD, awc, "sim_disk_wrsect", RKDEB_DAT & dptr->dctrl, RKDEB_OPS);
sim_disk_data_trace (uptr, (uint8 *)rkxb, da/RK_NUMWD, awc*sizeof(*rkxb), "sim_disk_wrsect", RKDEB_DAT & dptr->dctrl, RKDEB_OPS);
err = sim_disk_wrsect (uptr, da/RK_NUMWD, (uint8 *)rkxb, NULL, awc/RK_NUMWD);
}
break; /* end write */
@@ -817,7 +820,7 @@ if ((uptr->FUNC == RKCS_READ) && (rkcs & RKCS_FMT)) /* read format? */
else da = da + wc + (RK_NUMWD - 1); /* count by words */
track = (da / RK_NUMWD) / RK_NUMSC;
sect = (da / RK_NUMWD) % RK_NUMSC;
uptr->CYL = track / RK_NUMSF; /* update position */
uptr->CYL = track / RK_NUMSF;
rkda = (rkda & RKDA_DRIVE) | (track << RKDA_V_TRACK) | (sect << RKDA_V_SECT);
rk_set_done (0);
@@ -919,13 +922,9 @@ return auto_config (0, 0);
t_stat rk_attach (UNIT *uptr, CONST char *cptr)
{
t_stat r;
static const char *drives[] = {"RK05", NULL};
r = sim_disk_attach_ex2 (uptr, cptr, RK_NUMWD * sizeof (uint16),
sizeof (uint16), TRUE, 0,
"RK05", 0, 0,
(uptr->flags & UNIT_NOAUTO) ? NULL: drives,
RK_RSRVSEC);
"RK05", 0, 0, NULL, RK_RSRVSEC);
if (r != SCPE_OK) /* error? */
return r;
return SCPE_OK;

55
PDP11/pdp11_rq.c
View File

@@ -122,6 +122,12 @@ extern int32 MMR2;
#error "Assertion failure: RQ_NUMCT exceeds 4"
#endif
#if defined (VAX_610)
#define MICROVAX1 1
#else
#define MICROVAX1 0
#endif
#include "pdp11_uqssp.h"
#include "pdp11_mscp.h"
#include "sim_disk.h"
@@ -137,13 +143,7 @@ extern int32 MMR2;
#define RQ_SH_UN 010 /* show unit q's */
#define RQ_SH_ALL 017 /* show all */
#define RQ_CLASS 1 /* RQ class */
#define RQU_UQPM 6 /* UB port model */
#define RQQ_UQPM 19 /* QB port model */
#define RQ_UQPM (UNIBUS? RQU_UQPM: RQQ_UQPM)
#define RQU_MODEL 6 /* UB MSCP ctrl model (UDA50A) */
#define RQQ_MODEL 19 /* QB MSCP ctrl model (RQDX3) */
#define RQ_MODEL (UNIBUS? RQU_MODEL: RQQ_MODEL)
#define RQ_CLASS 1 /* RQ class: Mass storage controllers */
#define RQ_HVER 1 /* hardware version */
#define RQ_SVER 3 /* software version */
#define RQ_DHTMO 60 /* def host timeout */
@@ -172,6 +172,7 @@ extern int32 MMR2;
#define unit_plug u4 /* drive unit plug value */
#define io_status u5 /* io status from callback */
#define io_complete u6 /* io completion flag */
/* we can re-use filebuf because we don't set UNIT_BUFABLE in flags */
#define rqxb filebuf /* xfer buffer */
#define RQ_RMV(u) ((drv_tab[GET_DTYPE (u->flags)].flgs & RQDF_RMV)? \
UF_RMV: 0)
@@ -752,31 +753,35 @@ x RA73 70(+1) 21 2667+ 21 1 ? 3920490
// AFAIK the UNIBUS KLESI and QBUS KLESI used the same controller type ...
#define KLESI_CTYPE 1 // RC25 controller (UNIBUS and QBUS both)
#define KLESI_UQPM 1
#define KLESI_MODEL 1
#define KLESI_UQPM 3
#define KLESI_MODEL 3
#define RUX50_CTYPE 2 // UNIBUS RX50-only controller
#define RUX50_UQPM 2
#define RUX50_MODEL 2
#define RUX50_UQPM 10 // this should be 10 according to the MSCP spec
#define RUX50_MODEL 10
#define UDA50_CTYPE 3 // UNIBUS SDI (RAxx) controller
#define UDA50_UQPM 6
#define UDA50_UQPM 6 // really type of UDA50A; UDA50 is 2
#define UDA50_MODEL 6
#define RQDX3_CTYPE 4 // QBUS RX50/RDxx controller
#define RQDX1_CTYPE 4 // QBUS RX50/RDxx controller,
#define RQDX1_UQPM 7 // first version; RQDX2 has the same id
#define RQDX1_MODEL 7
#define RQDX3_CTYPE 5 // QBUS RX50/RDxx controller
#define RQDX3_UQPM 19
#define RQDX3_MODEL 19
#define KDA50_CTYPE 5 // QBUS SDI (RAxx) controller
#define KDA50_UQPM 13
#define KDA50_CTYPE 6 // QBUS SDI (RAxx) controller
#define KDA50_UQPM 13 // KDA50-Q
#define KDA50_MODEL 13
#define KRQ50_CTYPE 6 // QBUS RRD40/50 CDROM controller
#define KRQ50_CTYPE 7 // QBUS RRD40/50 CDROM controller
#define KRQ50_UQPM 16
#define KRQ50_MODEL 16
#define KRU50_CTYPE 7 // UNIBUS RRD40/50 CDROM controller
#define KRU50_UQPM 26
#define KRU50_CTYPE 8 // UNIBUS RRD40/50 CDROM controller
#define KRU50_UQPM 26 // unassigned in appendix C
#define KRU50_MODEL 26
struct drvtyp {
@@ -883,6 +888,7 @@ static struct ctlrtyp ctlr_tab[] = {
RQ_CTLR (KLESI),
RQ_CTLR (RUX50),
RQ_CTLR (UDA50),
RQ_CTLR (RQDX1),
RQ_CTLR (RQDX3),
RQ_CTLR (KDA50),
RQ_CTLR (KRQ50),
@@ -1119,10 +1125,12 @@ MTAB rq_mod[] = {
NULL, &rq_show_ctrl, NULL, "Display all unit queues" },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO, RQ_SH_ALL, "ALL", NULL,
NULL, &rq_show_ctrl, NULL, "Display complete controller state" },
{ MTAB_XTD|MTAB_VDV, RQDX1_CTYPE, NULL, "RQDX1",
&rq_set_ctype, NULL, NULL, "Set RQDX1/2 (QBUS RX50/RDnn) Controller Type" },
{ MTAB_XTD|MTAB_VDV, RQDX3_CTYPE, NULL, "RQDX3",
&rq_set_ctype, NULL, NULL, "Set RQDX3 (QBUS RX50/RDnn) Controller Type" },
{ MTAB_XTD|MTAB_VDV, UDA50_CTYPE, NULL, "UDA50",
&rq_set_ctype, NULL, NULL, "Set UDA50 (UNIBUS SDI RAnn) Controller Type" },
&rq_set_ctype, NULL, NULL, "Set UDA50A (UNIBUS SDI RAnn) Controller Type" },
{ MTAB_XTD|MTAB_VDV, KDA50_CTYPE, NULL, "KDA50",
&rq_set_ctype, NULL, NULL, "Set KDA50 (QBUS SDI RAnn) Controller Type" },
{ MTAB_XTD|MTAB_VDV, KRQ50_CTYPE, NULL, "KRQ50",
@@ -3099,7 +3107,8 @@ if (cidx < 0) /* not found??? */
cp = rq_ctxmap[cidx]; /* get context */
cp->cnum = cidx; /* init index */
if (cp->ctype == DEFAULT_CTYPE)
cp->ctype = (UNIBUS? UDA50_CTYPE : RQDX3_CTYPE);
cp->ctype = (UNIBUS ? UDA50_CTYPE :
MICROVAX1 ? RQDX1_CTYPE : RQDX3_CTYPE);
if (!plugs_inited ) {
#if !defined (VM_VAX)
@@ -3418,9 +3427,9 @@ fprintf (st, "UDA50 MSCP Disk Controller (%s)\n\n", dptr->name);
fprintf (st, "The simulator implements four MSCP disk controllers, RQ, RQB, RQC, RQD.\n");
fprintf (st, "Initially, RQB, RQC, and RQD are disabled. Each RQ controller simulates\n");
fprintf (st, "an MSCP disk controller with four drives. The MSCP controller type can be\n");
fprintf (st, "specified as one of RQDX3, UDA50, KDA50, KRQ50, KLESI or RUX50. RQ options\n");
fprintf (st, "include the ability to set units write enabled or write locked, and to set\n");
fprintf (st, "the drive type to one of many disk types:\n");
fprintf (st, "specified as one of RQDX1, RQDX3, UDA50, KDA50, KRQ50, KLESI or RUX50.\n");
fprintf (st, "RQ options include the ability to set units write enabled or write locked,\n");
fprintf (st, "and to set the drive type to one of many disk types:\n");
fprint_set_help (st, dptr);
fprintf (st, "set RQn RAUSER{=n} Set disk type to RA82 with n MB's\n");
fprintf (st, " (1MB is 1000000 bytes)\n");