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Notes For V3.1-0
RESTRICTION: The FP15 and XVM features of the PDP-15 are only partially debugged. Do NOT enable these features for normal operations. 1. New Features in 3.1-0 1.1 SCP and libraries - Added simulated Ethernet support for VMS, FreeBSD, Mac OS/X. - Added status return to tmxr_putc_ln. - Added sim_putchar_s to handle possible output stalls. 1.2 All DECtapes - Added "DECtape off reel" error stop. 1.3 All Asynchronous Consoles - Added support for output congestion stall if using a Telnet connection. 1.4 PDP-1 - Added Type 23 parallel drum support. 1.5 PDP-8 - Added instruction history. - Added TSC8-75 option support for ETOS. - Added TD8E DECtape support. 1.6 PDP-18b - Added instruction history. - Changed PDP-9, PDP-15 API default to enabled. 1.7 PDP-11 - Added support for 18b only Qbus devices. - Formalized bus and addressing definitions. - Added control to enable/disable autoconfiguration. - Added stub support for second Unibus Ethernet controller. 1.7 Interdata 32b - Added instruction history. 1.8 Eclipse - Added floating point support. - Added programmable interval timer support. 1.9 H316 - Added DMA/DMC support. - Added fixed head disk support. - Added moving head disk support. - Added magtape support. 1.10 IBM 1130 (Brian Knittel) - Added support for physical card reader, using the Cardread interface (www.ibm1130.org/sim/downloads). - Added support for physical printer (flushes output buffer after each line). 2. Bugs Fixed in 3.1-0 2.1 SCP and libraries - Fixed numerous bugs in Ethernet library. 2.2 All DECtapes - Fixed reverse checksum value in 'read all' mode. - Simplified (and sped up) timing. 2.3 PDP-8 - Fixed bug in RX28 read status (found by Charles Dickman). - Fixed RX28 double density write. 2.4 PDP-18b - Fixed autoincrement bug in PDP-4, PDP-7, PDP-9. 2.5 PDP-11/VAX - Revised RQ MB->LBN conversion for greater accuracy. - Fixed bug in IO configuration (found by David Hittner). - Fixed bug with multiple RQ RAUSER drives. - Fixed bug in second Qbus Ethernet controller interrupts. 2.6 Nova/Eclipse - Fixed bugs in DKP flag clear, map setup, map usage (Charles Owen). - Fixed bug in MT, reset completes despite I/O reset (Charles Owen). - Fixed bug in MT, space operations return word count (Charles Owen). 2.7 IBM 1130 (Brian Knittel) - Fixed bug in setting carry bit in subtract and subtract double. - Fixed timing problem in console printer simulation. 2.8 1620 - Fixed bug in branch digit (found by Dave Babcock). 3. New Features in 3.0 vs prior releases 3.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support. 3.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 3.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 3.4 PDP-1 - Added block loader format support to LOAD. - Changed BOOT PTR to allow loading of all of the first bank of memory. - The LOAD command takes an optional argument specifying the memory field to be loaded. - The PTR BOOT command takes its starting memory field from the TA (address switch) register. 3.5 PDP-18b Family - Added PDP-4 EAE support. - Added PDP-15 FP15 support. - Added PDP-15 XVM support. - Added PDP-15 "re-entrancy ECO". - Added PDP-7, PDP-9, PDP-15 hardware RIM loader support in BOOT PTR. 4. Bugs Fixed in 3.0 vs prior releases 4.1 SCP and Libraries - Fixed end of file problem in dep, idep. - Fixed handling of trailing spaces in dep, idep. 4.2 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). - Fixed bug in user disk size (found by Chaskiel M Grundman). 4.3 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. - Revised fetch to model hardware more closely. - Fixed tape read end-of-record handling based on real 1401. - Added diagnostic read (space forward). 4.4 Nova - Fixed DSK variable size interaction with restore. - Fixed bug in DSK set size routine. 4.5 PDP-1 - Fixed DT variable size interaction with restore. - Updated CPU, line printer, standard devices to detect indefinite I/O wait. - Fixed incorrect logical, missing activate, break in drum simulator. - Fixed bugs in instruction decoding, overprinting for line printer. - Fixed system hang if continue after PTR error. - Fixed PTR to start/stop on successive rpa instructions. 4.6 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. - Fixed bug in user disk size (found by Chaskiel M Grundman). 4.7 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. - Fixed bug in PDP-4 line printer overprinting. - Fixed bug in PDP-15 memory protect/skip interaction. - Fixed bug in RF set size routine. - Increased PTP TIME for PDP-15 operating systems. - Fixed priorities in PDP-15 API (differs from PDP-9). - Fixed sign handling in PDP-15 EAE unsigned mul/div (differs from PDP-9). - Fixed bug in CAF, clears API subsystem. 4.8 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. - Fixed bug in DF, RF set size routine. 4.9 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. - Fixed DR drum sizes. - Fixed DR variable capacity interaction with SAVE/RESTORE. 4.10 GRI - Fixed bug in SC queue pointer management. 4.11 PDP-10 - Fixed bug in RP read header. 4.12 Ibm1130 - Fixed bugs found by APL 1130. 4.13 Altairz80 - Fixed bug in real-time clock on Windows host. 4.14 1620 - Fixed bug in immediate index add (found by Michael Short).
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
b2101ecdd4
commit
1da2d9452d
362
PDP8/pdp8_cpu.c
362
PDP8/pdp8_cpu.c
@@ -1,6 +1,6 @@
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/* pdp8_cpu.c: PDP-8 CPU simulator
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Copyright (c) 1993-2003, Robert M Supnik
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Copyright (c) 1993-2004, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,9 @@
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cpu central processor
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31-Dec-03 RMS Fixed bug in set_cpu_hist
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13-Oct-03 RMS Added instruction history
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Added TSC8-75 support (from Bernhard Baehr)
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12-Mar-03 RMS Added logical name support
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04-Oct-02 RMS Revamped device dispatching, added device number support
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06-Jan-02 RMS Added device enable/disable routines
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@@ -184,12 +187,23 @@
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#define PCQ_SIZE 64 /* must be 2**n */
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = MA
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#define UNIT_V_NOEAE (UNIT_V_UF) /* EAE absent */
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#define UNIT_NOEAE (1 << UNIT_V_NOEAE)
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#define UNIT_V_MSIZE (UNIT_V_UF+1) /* dummy mask */
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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#define HIST_PC 0x40000000
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#define HIST_MIN 64
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#define HIST_MAX 65536
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struct InstHistory {
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int32 pc;
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int32 ea;
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int16 ir;
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int16 opnd;
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int16 lac;
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int16 mq; };
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uint16 M[MAXMEMSIZE] = { 0 }; /* main memory */
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int32 saved_LAC = 0; /* saved L'AC */
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int32 saved_MQ = 0; /* saved MQ */
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@@ -203,6 +217,10 @@ int32 SC = 0; /* EAE shift count */
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int32 UB = 0; /* User mode Buffer */
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int32 UF = 0; /* User mode Flag */
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int32 OSR = 0; /* Switch Register */
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int32 tsc_ir = 0; /* TSC8-75 IR */
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int32 tsc_pc = 0; /* TSC8-75 PC */
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int32 tsc_cdf = 0; /* TSC8-75 CDF flag */
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int32 tsc_enb = 0; /* TSC8-75 enabled */
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int16 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
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int32 pcq_p = 0; /* PC queue ptr */
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REG *pcq_r = NULL; /* PC queue reg ptr */
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@@ -211,6 +229,9 @@ int32 int_enable = INT_INIT_ENABLE; /* intr enables */
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int32 int_req = 0; /* intr requests */
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int32 stop_inst = 0; /* trap on ill inst */
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int32 (*dev_tab[DEV_MAX])(int32 IR, int32 dat); /* device dispatch */
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int32 hst_p = 0; /* history pointer */
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int32 hst_lnt = 0; /* history length */
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struct InstHistory *hst = NULL; /* instruction history */
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extern int32 sim_interval;
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extern int32 sim_int_char;
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@@ -223,6 +244,8 @@ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
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t_stat cpu_reset (DEVICE *dptr);
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_bool build_dev_tab (void);
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/* CPU data structures
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@@ -275,6 +298,8 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 24576, NULL, "24K", &cpu_set_size },
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{ UNIT_MSIZE, 28672, NULL, "28K", &cpu_set_size },
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{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "HISTORY", "HISTORY",
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&cpu_set_hist, &cpu_show_hist },
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{ 0 } };
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DEVICE cpu_dev = {
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@@ -335,9 +360,8 @@ sim_interval = sim_interval - 1;
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major opcode. For IOT, the extra decode points are not useful;
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for OPR, only the group flag (IR<3>) is used.
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The following macros define the address calculations for data and
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jump calculations. Data calculations return a full 15b extended
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address, jump calculations a 12b field-relative address.
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AND, TAD, ISZ, DCA calculate a full 15b effective address.
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JMS, JMP calculate a 12b field-relative effective address.
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Autoindex calculations always occur within the same field as the
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instruction fetch. The field must exist; otherwise, the instruction
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@@ -346,84 +370,103 @@ sim_interval = sim_interval - 1;
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Note that MA contains IF'PC.
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*/
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#define ZERO_PAGE MA = IF | (IR & 0177)
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#define CURR_PAGE MA = (MA & 077600) | (IR & 0177)
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#define INDIRECT if ((MA & 07770) != 00010) MA = DF | M[MA]; \
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777)
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if (hst_lnt) { /* history enabled? */
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int32 ea;
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#define ZERO_PAGE_J MA = IR & 0177
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#define CURR_PAGE_J MA = (MA & 007600) | (IR & 0177)
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#define INDIRECT_J if ((MA & 07770) != 00010) MA = M[MA]; \
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else MA = (M[MA] = (M[MA] + 1) & 07777)
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#define CHANGE_FIELD IF = IB; UF = UB; \
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int_req = int_req | INT_NO_CIF_PENDING
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hst_p = (hst_p + 1); /* next entry */
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if (hst_p >= hst_lnt) hst_p = 0;
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hst[hst_p].pc = MA | HIST_PC; /* save PC, IR, LAC, MQ */
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hst[hst_p].ir = IR;
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hst[hst_p].lac = LAC;
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hst[hst_p].mq = MQ;
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if (IR < 06000) { /* mem ref? */
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if (IR & 0200) ea = (MA & 077600) | (IR & 0177);
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else ea = IF | (IR & 0177); /* direct addr */
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if (IR & 0400) { /* indirect? */
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if (IR < 04000) { /* mem operand? */
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if ((ea & 07770) != 00010) ea = DF | M[ea];
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else ea = DF | ((M[ea] + 1) & 07777); }
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else { /* no, jms/jmp */
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if ((ea & 07770) != 00010) ea = IB | M[ea];
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else ea = IB | ((M[ea] + 1) & 07777); }
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}
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hst[hst_p].ea = ea; /* save eff addr */
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hst[hst_p].opnd = M[ea]; /* save operand */
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}
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}
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switch ((IR >> 7) & 037) { /* decode IR<0:4> */
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/* Opcode 0, AND */
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case 000: /* AND, dir, zero */
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ZERO_PAGE;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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LAC = LAC & (M[MA] | 010000);
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break;
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case 001: /* AND, dir, curr */
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CURR_PAGE;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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LAC = LAC & (M[MA] | 010000);
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break;
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case 002: /* AND, indir, zero */
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ZERO_PAGE;
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INDIRECT;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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LAC = LAC & (M[MA] | 010000);
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break;
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case 003: /* AND, indir, curr */
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CURR_PAGE;
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INDIRECT;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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LAC = LAC & (M[MA] | 010000);
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break;
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/* Opcode 1, TAD */
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case 004: /* TAD, dir, zero */
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ZERO_PAGE;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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LAC = (LAC + M[MA]) & 017777;
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break;
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case 005: /* TAD, dir, curr */
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CURR_PAGE;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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LAC = (LAC + M[MA]) & 017777;
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break;
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case 006: /* TAD, indir, zero */
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ZERO_PAGE;
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INDIRECT;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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LAC = (LAC + M[MA]) & 017777;
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break;
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case 007: /* TAD, indir, curr */
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CURR_PAGE;
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INDIRECT;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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LAC = (LAC + M[MA]) & 017777;
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break;
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/* Opcode 2, ISZ */
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case 010: /* ISZ, dir, zero */
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ZERO_PAGE;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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M[MA] = MB = (M[MA] + 1) & 07777; /* field must exist */
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if (MB == 0) PC = (PC + 1) & 07777;
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break;
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case 011: /* ISZ, dir, curr */
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CURR_PAGE;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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M[MA] = MB = (M[MA] + 1) & 07777; /* field must exist */
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if (MB == 0) PC = (PC + 1) & 07777;
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break;
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case 012: /* ISZ, indir, zero */
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ZERO_PAGE;
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INDIRECT;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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MB = (M[MA] + 1) & 07777;
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if (MEM_ADDR_OK (MA)) M[MA] = MB;
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if (MB == 0) PC = (PC + 1) & 07777;
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break;
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case 013: /* ISZ, indir, curr */
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CURR_PAGE;
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INDIRECT;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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MB = (M[MA] + 1) & 07777;
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if (MEM_ADDR_OK (MA)) M[MA] = MB;
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if (MB == 0) PC = (PC + 1) & 07777;
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@@ -432,91 +475,178 @@ case 013: /* ISZ, indir, curr */
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/* Opcode 3, DCA */
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case 014: /* DCA, dir, zero */
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ZERO_PAGE;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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M[MA] = LAC & 07777;
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LAC = LAC & 010000;
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break;
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case 015: /* DCA, dir, curr */
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CURR_PAGE;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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M[MA] = LAC & 07777;
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LAC = LAC & 010000;
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break;
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case 016: /* DCA, indir, zero */
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ZERO_PAGE;
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INDIRECT;
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MA = IF | (IR & 0177); /* dir addr, page zero */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
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LAC = LAC & 010000;
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break;
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case 017: /* DCA, indir, curr */
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CURR_PAGE;
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INDIRECT;
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MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
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if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
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else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
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if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
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LAC = LAC & 010000;
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break;
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/* Opcode 4, JMS */
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/* Opcode 4, JMS. From Bernhard Baehr's description of the TSC8-75:
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(In user mode) the current JMS opcode is moved to the ERIOT register, the ECDF
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flag is cleared. The address of the JMS instruction is loaded into the ERTB
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register and the TSC8-75 I/O flag is raised. When the TSC8-75 is enabled, the
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target addess of the JMS is loaded into PC, but nothing else (loading of IF, UF,
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clearing the interrupt inhibit flag, storing of the return address in the first
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word of the subroutine) happens. When the TSC8-75 is disabled, the JMS is performed
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as usual. */
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case 020: /* JMS, dir, zero */
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ZERO_PAGE_J;
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CHANGE_FIELD;
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MA = IF | MA;
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PCQ_ENTRY;
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if (MEM_ADDR_OK (MA)) M[MA] = PC;
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MA = IR & 0177; /* dir addr, page zero */
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if (UF) { /* user mode? */
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tsc_ir = IR; /* save instruction */
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tsc_cdf = 0; } /* clear flag */
|
||||
if (UF && tsc_enb) { /* user mode, TSC enab? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } /* request intr */
|
||||
else { /* normal */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
MA = IF | MA;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC; }
|
||||
PC = (MA + 1) & 07777;
|
||||
break;
|
||||
case 021: /* JMS, dir, curr */
|
||||
CURR_PAGE_J;
|
||||
CHANGE_FIELD;
|
||||
MA = IF | MA;
|
||||
PCQ_ENTRY;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||||
MA = (MA & 007600) | (IR & 0177); /* dir addr, curr page */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; } /* clear flag */
|
||||
if (UF && tsc_enb) { /* user mode, TSC enab? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } /* request intr */
|
||||
else { /* normal */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
MA = IF | MA;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC; }
|
||||
PC = (MA + 1) & 07777;
|
||||
break;
|
||||
case 022: /* JMS, indir, zero */
|
||||
ZERO_PAGE;
|
||||
INDIRECT_J;
|
||||
CHANGE_FIELD;
|
||||
MA = IF | MA;
|
||||
PCQ_ENTRY;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||||
MA = IF | (IR & 0177); /* dir addr, page zero */
|
||||
if ((MA & 07770) != 00010) MA = M[MA]; /* indirect; autoinc? */
|
||||
else MA = (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; } /* clear flag */
|
||||
if (UF && tsc_enb) { /* user mode, TSC enab? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } /* request intr */
|
||||
else { /* normal */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
MA = IF | MA;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC; }
|
||||
PC = (MA + 1) & 07777;
|
||||
break;
|
||||
case 023: /* JMS, indir, curr */
|
||||
CURR_PAGE;
|
||||
INDIRECT_J;
|
||||
CHANGE_FIELD;
|
||||
MA = IF | MA;
|
||||
PCQ_ENTRY;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC;
|
||||
MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
|
||||
if ((MA & 07770) != 00010) MA = M[MA]; /* indirect; autoinc? */
|
||||
else MA = (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; } /* clear flag */
|
||||
if (UF && tsc_enb) { /* user mode, TSC enab? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } /* request intr */
|
||||
else { /* normal */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
MA = IF | MA;
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = PC; }
|
||||
PC = (MA + 1) & 07777;
|
||||
break;
|
||||
|
||||
/* Opcode 5, JMP. From Bernhard Baehr's description of the TSC8-75:
|
||||
|
||||
/* Opcode 5, JMP */
|
||||
(In user mode) the current JMP opcode is moved to the ERIOT register, the ECDF
|
||||
flag is cleared. The address of the JMP instruction is loaded into the ERTB
|
||||
register and the TSC8-75 I/O flag is raised. Then the JMP is performed as usual
|
||||
(including the setting of IF, UF and clearing the interrupt inhibit flag). */
|
||||
|
||||
case 024: /* JMP, dir, zero */
|
||||
ZERO_PAGE_J;
|
||||
CHANGE_FIELD;
|
||||
PCQ_ENTRY;
|
||||
MA = IR & 0177; /* dir addr, page zero */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; /* clear flag */
|
||||
if (tsc_enb) { /* TSC8 enabled? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } } /* request intr */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
PC = MA;
|
||||
break;
|
||||
case 025: /* JMP, dir, curr */
|
||||
CURR_PAGE_J;
|
||||
CHANGE_FIELD;
|
||||
PCQ_ENTRY;
|
||||
MA = (MA & 007600) | (IR & 0177); /* dir addr, curr page */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; /* clear flag */
|
||||
if (tsc_enb) { /* TSC8 enabled? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } } /* request intr */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
PC = MA;
|
||||
break;
|
||||
case 026: /* JMP, indir, zero */
|
||||
ZERO_PAGE;
|
||||
INDIRECT_J;
|
||||
CHANGE_FIELD;
|
||||
PCQ_ENTRY;
|
||||
MA = IF | (IR & 0177); /* dir addr, page zero */
|
||||
if ((MA & 07770) != 00010) MA = M[MA]; /* indirect; autoinc? */
|
||||
else MA = (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; /* clear flag */
|
||||
if (tsc_enb) { /* TSC8 enabled? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } } /* request intr */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
PC = MA;
|
||||
break;
|
||||
case 027: /* JMP, indir, curr */
|
||||
CURR_PAGE;
|
||||
INDIRECT_J;
|
||||
CHANGE_FIELD;
|
||||
PCQ_ENTRY;
|
||||
MA = (MA & 077600) | (IR & 0177); /* dir addr, curr page */
|
||||
if ((MA & 07770) != 00010) MA = M[MA]; /* indirect; autoinc? */
|
||||
else MA = (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
if (UF) { /* user mode? */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; /* clear flag */
|
||||
if (tsc_enb) { /* TSC8 enabled? */
|
||||
tsc_pc = (PC - 1) & 07777; /* save PC */
|
||||
int_req = int_req | INT_TSC; } } /* request intr */
|
||||
IF = IB; /* change IF */
|
||||
UF = UB; /* change UF */
|
||||
int_req = int_req | INT_NO_CIF_PENDING; /* clr intr inhibit */
|
||||
PC = MA;
|
||||
break;
|
||||
|
||||
@@ -601,7 +731,11 @@ case 034:case 035: /* OPR, group 1 */
|
||||
break; } /* uses address path */
|
||||
break; /* end group 1 */
|
||||
|
||||
/* OPR group 2 */
|
||||
/* OPR group 2. From Bernhard Baehr's description of the TSC8-75:
|
||||
|
||||
(In user mode) HLT (7402), OSR (7404) and microprogrammed combinations with
|
||||
HLT and OSR: Additional to raising a user mode interrupt, the current OPR
|
||||
opcode is moved to the ERIOT register and the ECDF flag is cleared. */
|
||||
|
||||
case 036:case 037: /* OPR, groups 2, 3 */
|
||||
if ((IR & 01) == 0) { /* group 2 */
|
||||
@@ -657,7 +791,10 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
if ((LAC < 04000) && (LAC != 0)) PC = (PC + 1) & 07777;
|
||||
break; } /* end switch skips */
|
||||
if (IR & 0200) LAC = LAC & 010000; /* CLA */
|
||||
if ((IR & 06) && UF) int_req = int_req | INT_UF;
|
||||
if ((IR & 06) && UF) { /* user mode? */
|
||||
int_req = int_req | INT_UF; /* request intr */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
tsc_cdf = 0; } /* clear flag */
|
||||
else {
|
||||
if (IR & 04) LAC = LAC | OSR; /* OSR */
|
||||
if (IR & 02) reason = STOP_HALT; } /* HLT */
|
||||
@@ -745,7 +882,8 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
case 021: /* mode B: DAD */
|
||||
if (emode) {
|
||||
MA = IF | PC;
|
||||
INDIRECT; /* defer state */
|
||||
if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
|
||||
else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
MQ = MQ + M[MA];
|
||||
MA = DF | ((MA + 1) & 07777);
|
||||
LAC = (LAC & 07777) + M[MA] + (MQ >> 12);
|
||||
@@ -764,7 +902,8 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
case 022: /* mode B: DST */
|
||||
if (emode) {
|
||||
MA = IF | PC;
|
||||
INDIRECT; /* defer state */
|
||||
if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
|
||||
else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = MQ & 07777;
|
||||
MA = DF | ((MA + 1) & 07777);
|
||||
if (MEM_ADDR_OK (MA)) M[MA] = LAC & 07777;
|
||||
@@ -773,7 +912,10 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
LAC = LAC | SC; /* mode A: SCA then */
|
||||
case 002: /* MUY */
|
||||
MA = IF | PC;
|
||||
if (emode) { INDIRECT; } /* mode B: defer */
|
||||
if (emode) { /* mode B: defer */
|
||||
if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
|
||||
else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
}
|
||||
temp = (MQ * M[MA]) + (LAC & 07777);
|
||||
LAC = (temp >> 12) & 07777;
|
||||
MQ = temp & 07777;
|
||||
@@ -788,7 +930,10 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
LAC = LAC | SC; /* mode A: SCA then */
|
||||
case 003: /* DVI */
|
||||
MA = IF | PC;
|
||||
if (emode) { INDIRECT; } /* mode B: defer */
|
||||
if (emode) { /* mode B: defer */
|
||||
if ((MA & 07770) != 00010) MA = DF | M[MA]; /* indirect; autoinc? */
|
||||
else MA = DF | (M[MA] = (M[MA] + 1) & 07777); /* incr before use */
|
||||
}
|
||||
if ((LAC & 07777) >= M[MA]) { /* overflow? */
|
||||
LAC = LAC | 010000; /* set link */
|
||||
MQ = ((MQ << 1) + 1) & 07777; /* rotate MQ */
|
||||
@@ -873,11 +1018,18 @@ case 036:case 037: /* OPR, groups 2, 3 */
|
||||
break; } /* end switch */
|
||||
break; /* end case 7 */
|
||||
|
||||
/* Opcode 6, IOT */
|
||||
/* Opcode 6, IOT. From Bernhard Baehr's description of the TSC8-75:
|
||||
|
||||
(In user mode) Additional to raising a user mode interrupt, the current IOT
|
||||
opcode is moved to the ERIOT register. When the IOT is a CDF instruction (62x1),
|
||||
the ECDF flag is set, otherwise it is cleared. */
|
||||
|
||||
case 030:case 031:case 032:case 033: /* IOT */
|
||||
if (UF) { /* privileged? */
|
||||
int_req = int_req | INT_UF;
|
||||
int_req = int_req | INT_UF; /* request intr */
|
||||
tsc_ir = IR; /* save instruction */
|
||||
if ((IR & 07707) == 06201) tsc_cdf = 1; /* set/clear flag */
|
||||
else tsc_cdf = 0;
|
||||
break; }
|
||||
device = (IR >> 3) & 077; /* device = IR<3:8> */
|
||||
pulse = IR & 07; /* pulse = IR<9:11> */
|
||||
@@ -922,6 +1074,7 @@ case 030:case 031:case 032:case 033: /* IOT */
|
||||
dev_done = 0;
|
||||
int_enable = INT_INIT_ENABLE;
|
||||
LAC = 0;
|
||||
reset_all (1); /* reset all dev */
|
||||
break; } /* end switch pulse */
|
||||
break; /* end case 0 */
|
||||
|
||||
@@ -1143,3 +1296,58 @@ for (i = 0; (dptr = sim_devices[i]) != NULL; i++) { /* add devices */
|
||||
} /* end for i */
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
/* Set history */
|
||||
|
||||
t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
int32 i, lnt;
|
||||
t_stat r;
|
||||
|
||||
if (cptr == NULL) {
|
||||
for (i = 0; i < hst_lnt; i++) hst[i].pc = 0;
|
||||
hst_p = 0;
|
||||
return SCPE_OK; }
|
||||
lnt = (int32) get_uint (cptr, 10, HIST_MAX, &r);
|
||||
if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) return SCPE_ARG;
|
||||
hst_p = 0;
|
||||
if (hst_lnt) {
|
||||
free (hst);
|
||||
hst_lnt = 0;
|
||||
hst = NULL; }
|
||||
if (lnt) {
|
||||
hst = calloc (sizeof (struct InstHistory), lnt);
|
||||
if (hst == NULL) return SCPE_MEM;
|
||||
hst_lnt = lnt; }
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Show history */
|
||||
|
||||
t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
int32 l, k, di;
|
||||
t_value sim_eval;
|
||||
struct InstHistory *h;
|
||||
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
|
||||
UNIT *uptr, int32 sw);
|
||||
|
||||
if (hst_lnt == 0) return SCPE_NOFNC; /* enabled? */
|
||||
fprintf (st, "PC L AC MQ ea IR\n\n");
|
||||
di = hst_p; /* work forward */
|
||||
for (k = 0; k < hst_lnt; k++) { /* print specified */
|
||||
h = &hst[(++di) % hst_lnt]; /* entry pointer */
|
||||
if (h->pc & HIST_PC) { /* instruction? */
|
||||
l = (h->lac >> 12) & 1; /* link */
|
||||
fprintf (st, "%05o %o %04o %04o ", h->pc & ADDRMASK, l, h->lac & 07777, h->mq);
|
||||
if (h->ir < 06000) fprintf (st, "%05o ", h->ea);
|
||||
else fprintf (st, " ");
|
||||
sim_eval = h->ir;
|
||||
if ((fprint_sym (st, h->pc & ADDRMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
|
||||
fprintf (st, "(undefined) %04o", h->ir);
|
||||
if (h->ir < 04000) fprintf (st, " [%04o]", h->opnd);
|
||||
fputc ('\n', st); /* end line */
|
||||
} /* end else instruction */
|
||||
} /* end for */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user