Notes For V3.2-3

RESTRICTION: The PDP-15 FPP is only partially debugged.  Do NOT
enable this feature for normal operations.
RESTRICTION: The HP DS disk is not debugged.  DO NOT enable this
feature for normal operations.

1. New Features in 3.2-3

1.1 SCP

- Added ECHO command (from Dave Bryan)

2. Bugs Fixed in 3.2-2

2.1 SCP

- Qualified RESTORE detach with SIM_SW_REST
- Fixed OS/2 issues in sim_console.c and sim_sock.h

2.2 HP2100 (all from Dave Bryan)

- Changed CPU error stops to report PC not PC + 1

- Fixed CLC to DR to stop operation in progress

- Functional and timing fixes to DP
  > controller sets ATN for all commands except read status
  > controller resumes polling for ATN interrupts after read status
  > check status on unattached drive set busy and not ready
  > check status tests wrong unit for write protect status
  > drive on line sets ATN, will set FLG if polling

- Functional and timing fixes to MS
  > fixed erroneous execution of rejected command
  > fixed erroneous execution of select-only command
  > fixed erroneous execution of clear command
  > fixed odd byte handling for read
  > fixed spurious odd byte status on 13183A EOF
  > modified handling of end of medium
  > added detailed timing, with fast and realistic modes
  > added reel sizes to simulate end of tape
  > added debug printouts

- Modified MT handling of end of medium

- Added tab to TTY control char set

2.3 VAX

- VAX RQ controllers start LUNs at 0 (from Andreas Cejna)
- Added compatibility mode definitions
- Fixed EMODD, EMODG to probe second longword of quadword destination

VAX/vax_cpu.c

@@ -25,6 +25,7 @@
 
    cpu		CVAX central processor
 
+   02-Sep-04	RMS	Fixed bug in EMODD/G, second word of quad dst not probed
    28-Jun-04	RMS	Fixed bug in DIVBx, DIVWx (reported by Peter Trimmel)
    18-Apr-04	RMS	Added octaword macros
    25-Jan-04	RMS	Removed local debug logging support
@@ -333,7 +334,7 @@ extern int32 op_emodg (int32 *opnd, int32 *rh, int32 *intgr, int32 *flg);
 extern void op_polyf (int32 *opnd, int32 acc);
 extern void op_polyd (int32 *opnd, int32 acc);
 extern void op_polyg (int32 *opnd, int32 acc);
-extern int32 op_emulate (int32 *opnd, int32 cc, int32 opc, int32 acc);
+extern int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc);
 extern int32 intexc (int32 vec, int32 cc, int32 ipl, int ei);
 extern int32 Read (uint32 va, int32 lnt, int32 acc);
 extern void Write (uint32 va, int32 val, int32 lnt, int32 acc);
@@ -497,11 +498,14 @@ else if (abortval < 0) {				/* mm or rsrv or int */
 	temp = fault_PC - PC;				/* delta PC if needed */
 	SETPC (fault_PC);				/* restore PC */
 	switch (-abortval) {				/* case on abort code */
-	case SCB_RESIN: case SCB_RESAD: case SCB_RESOP:	/* reserved fault */
+	case SCB_RESIN:					/* rsrv inst fault */
+	case SCB_RESAD:					/* rsrv addr fault */
+	case SCB_RESOP:					/* rsrv opnd fault */
 	    if (in_ie) ABORT (STOP_INIE);		/* in exc? panic */
 	    cc = intexc (-abortval, cc, 0, IE_EXC);	/* take exception */
 	    GET_CUR;					/* PSL<cur> changed */
 	    break;
+	case SCB_CMODE:					/* comp mode fault */
 	case SCB_ARITH:					/* arithmetic fault */
 	    if (in_ie) ABORT (STOP_INIE);		/* in exc? panic */
 	    cc = intexc (-abortval, cc, 0, IE_EXC);	/* take exception */
@@ -511,7 +515,8 @@ else if (abortval < 0) {				/* mm or rsrv or int */
 	    SP = SP - 4;
 	    in_ie = 0;
 	    break;
-	case SCB_ACV: case SCB_TNV:			/* mem management */
+	case SCB_ACV:					/* ACV fault */
+	case SCB_TNV:					/* TNV fault */
 	    if (in_ie) {				/* in exception? */
 		if (PSL & PSL_IS) ABORT (STOP_INIE);	/* on is? panic */
 		cc = intexc (SCB_KSNV, cc, 0, IE_SVE);	/* ksnv */
@@ -1049,7 +1054,7 @@ if (hst_lnt) {
 	hst[hst_p].PSL = PSL | cc;
 	hst[hst_p].opc = opc;
 	hst[hst_p].brdest = brdisp + PC;
-	for (i = 0; i < (numspec & DR_NSPMASK); i++)
+	for (i = 0; i < OPND_SIZE; i++)
 	    hst[hst_p].opnd[i] = opnd[i];
 	hst_p = hst_p + 1;
 	if (hst_p >= hst_lnt) hst_p = 0;
@@ -2197,7 +2202,9 @@ case EMODF:
 
 case EMODD:
 	r = op_emodd (opnd, &rh, &temp, &flg);
-	if (op7 < 0) Read (op8, L_LONG, WA);
+	if (op7 < 0) {
+	    Read (op8, L_BYTE, WA);
+	    Read ((op8 + 7) & LMASK, L_BYTE, WA);  }
 	if (op5 >= 0) R[op5] = temp;
 	else Write (op6, temp, L_LONG, WA);
 	WRITE_Q (r, rh);
@@ -2207,7 +2214,9 @@ case EMODD:
 
 case EMODG:
 	r = op_emodg (opnd, &rh, &temp, &flg);
-	if (op7 < 0) Read (op8, L_LONG, WA);
+	if (op7 < 0) {
+	    Read (op8, L_BYTE, WA);
+	    Read ((op8 + 7) & LMASK, L_BYTE, WA);  }
 	if (op5 >= 0) R[op5] = temp;
 	else Write (op6, temp, L_LONG, WA);
 	WRITE_Q (r, rh);
@@ -2263,16 +2272,15 @@ case MFPR:
 	CC_IIZP_L (r);
 	break;
 
-/* Emulated instructions */
+/* Emulated CIS instructions */
 
 case CVTPL:
-	opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3];
 case MOVP: case CMPP3: case CMPP4: case CVTLP:
 case CVTPS: case CVTSP: case CVTTP: case CVTPT:
 case ADDP4: case ADDP6: case SUBP4: case SUBP6:
 case MULP: case DIVP: case ASHP: case CRC:
 case MOVTC: case MOVTUC: case MATCHC: case EDITPC:
-	cc = op_emulate (opnd, cc, opc, acc);
+	cc = op_cis (opnd, cc, opc, acc);
 	break;
 default:
 	RSVD_INST_FAULT;

VAX/vax_cpu1.c

@@ -1446,7 +1446,7 @@ default:						/* others */
 return val;
 }
 
-/* Emulated instructions
+/* Emulated CIS instructions
 
 	opnd[0:5] =	six operands to be pushed (if PSL<fpd> = 0)
 	cc	=	condition codes
@@ -1458,7 +1458,7 @@ return val;
    In both cases, the exception occurs in the current mode.
 */
 
-int32 op_emulate (int32 *opnd, int32 cc, int32 opc, int32 acc)
+int32 op_cis (int32 *opnd, int32 cc, int32 opc, int32 acc)
 {
 int32 vec;
 
@@ -1468,7 +1468,9 @@ if (PSL & PSL_FPD) {					/* FPD set? */
 	Write (SP - 4, PSL | cc, L_LONG, WA);		/* push PSL */
 	SP = SP - 8;					/* decr stk ptr */
 	vec = ReadLP ((SCBB + SCB_EMULFPD) & PAMASK);  }
-else {	Read (SP - 1, L_BYTE, WA);			/* wchk stack */
+else {	if (opc == CVTPL)				/* CVTPL? handle .wl */
+	    opnd[2] = (opnd[2] >= 0)? ~opnd[2]: opnd[3];
+	Read (SP - 1, L_BYTE, WA);			/* wchk stack */
 	Write (SP - 48, opc, L_LONG, WA);		/* push opcode */
 	Write (SP - 44, fault_PC, L_LONG, WA);		/* push old PC */
 	Write (SP - 40, opnd[0], L_LONG, WA);		/* push operands */

VAX/vax_defs.h

@@ -26,6 +26,8 @@
    The author gratefully acknowledges the help of Stephen Shirron, Antonio
    Carlini, and Kevin Peterson in providing specifications for the Qbus VAX's
 
+   30-Aug-04	RMS	Added octa, h_floating instructin definitions
+   24-Aug-04	RMS	Added compatibility mode definitions
    18-Apr-04	RMS	Added octa, fp, string definitions
    19-May-03	RMS	Revised for new conditional compilation scheme
    14-Jul-02	RMS	Added infinite loop message
@@ -60,7 +62,8 @@
 #define ABORT_MCHK	(-SCB_MCHK)			/* machine check */
 #define ABORT_RESIN	(-SCB_RESIN)			/* rsvd instruction */
 #define ABORT_RESAD	(-SCB_RESAD)			/* rsvd addr mode */
-#define ABORT_RESOP	(-SCB_RESOP)			/* rsvd operand */
+#define ABORT_RESOP	(-SCB_RESOP)			/* rsvd operand */	
+#define ABORT_CMODE	(-SCB_CMODE)			/* comp mode fault */
 #define ABORT_ARITH	(-SCB_ARITH)			/* arithmetic trap */
 #define ABORT_ACV	(-SCB_ACV)			/* access violation */
 #define ABORT_TNV	(-SCB_TNV)			/* transl not vaid */
@@ -71,6 +74,7 @@
 #define FLT_OVFL_FAULT	p1 = FLT_OVRFLO, ABORT (ABORT_ARITH)
 #define FLT_DZRO_FAULT	p1 = FLT_DIVZRO, ABORT (ABORT_ARITH)
 #define FLT_UNFL_FAULT	p1 = FLT_UNDFLO, ABORT (ABORT_ARITH)
+#define CMODE_FAULT(cd)	p1 = (cd), ABORT (ABORT_CMODE)
 #define MACH_CHECK(cd)	p1 = (cd), ABORT (ABORT_MCHK)
 
 /* Address space */
@@ -150,6 +154,8 @@
 
 /* PSL, PSW, and condition codes */
 
+#define PSL_V_CM	31				/* compatibility mode */
+#define PSL_CM		(1 << PSL_V_CM)
 #define PSL_V_TP	30				/* trace pending */
 #define PSL_TP		(1 << PSL_V_TP)
 #define PSL_V_FPD	27				/* first part done */
@@ -239,6 +245,10 @@
 #define TIR_TRAP	(TIR_M_TRAP << TIR_V_TRAP)
 #define TRAP_INTOV	(1 << TIR_V_TRAP)		/* integer overflow */
 #define TRAP_DIVZRO	(2 << TIR_V_TRAP)		/* divide by zero */
+#define TRAP_FLTOVF	(3 << TIR_V_TRAP)		/* flt overflow */
+#define TRAP_FLTDIV	(4 << TIR_V_TRAP)		/* flt/dec div by zero */
+#define TRAP_FLTUND	(5 << TIR_V_TRAP)		/* flt underflow */
+#define TRAP_DECOVF	(6 << TIR_V_TRAP)		/* decimal overflow */
 #define TRAP_SUBSCR	(7 << TIR_V_TRAP)		/* subscript range */
 #define SET_TRAP(x)	trpirq = (trpirq & PSL_M_IPL) | (x)
 #define CLR_TRAPS	trpirq = trpirq & ~TIR_TRAP
@@ -252,6 +262,50 @@
 #define FLT_DIVZRO	0x9				/* flt div by zero */
 #define FLT_UNDFLO	0xA				/* flt underflow */
 
+/* Compatability mode fault parameters */
+
+#define CMODE_RSVI	0x0				/* reserved instr */
+#define CMODE_BPT	0x1				/* BPT */
+#define CMODE_IOT	0x2				/* IOT */
+#define CMODE_EMT	0x3				/* EMT */
+#define CMODE_TRAP	0x4				/* TRAP */
+#define CMODE_ILLI	0x5				/* illegal instr */
+#define CMODE_ODD	0x6				/* odd address */
+
+/* EDITPC suboperators */
+
+#define EO_END		0x00				/* end */
+#define EO_END_FLOAT	0x01				/* end float */
+#define EO_CLR_SIGNIF	0x02				/* clear signif */
+#define EO_SET_SIGNIF	0x03				/* set signif */
+#define EO_STORE_SIGN	0x04				/* store sign */
+#define EO_LOAD_FILL	0x40				/* load fill */
+#define EO_LOAD_SIGN	0x41				/* load sign */
+#define EO_LOAD_PLUS	0x42				/* load sign if + */
+#define EO_LOAD_MINUS	0x43				/* load sign if - */
+#define EO_INSERT	0x44				/* insert */
+#define EO_BLANK_ZERO	0x45				/* blank zero */
+#define EO_REPL_SIGN	0x46				/* replace sign */
+#define EO_ADJUST_LNT	0x47				/* adjust length */
+#define EO_FILL		0x80				/* fill */
+#define EO_MOVE		0x90				/* move */
+#define EO_FLOAT	0xA0				/* float */
+#define EO_RPT_MASK	0x0F				/* rpt mask */
+#define EO_RPT_FLAG	0x80				/* rpt flag */
+
+/* EDITPC R2 packup parameters */
+
+#define ED_V_SIGN	8				/* sign */
+#define ED_M_SIGN	0xFF
+#define ED_SIGN		(ED_M_SIGN << ED_V_SIGN)
+#define ED_V_FILL	0				/* fill */
+#define ED_M_FILL	0xFF
+#define ED_FILL		(ED_M_FILL << ED_V_FILL)
+#define ED_GETSIGN(x)	(((x) >> ED_V_SIGN) & ED_M_SIGN)
+#define ED_GETFILL(x)	(((x) >> ED_V_FILL) & ED_M_FILL)
+#define ED_PUTSIGN(r,x)	(((r) & ~ED_SIGN) | (((x) << ED_V_SIGN) & ED_SIGN))
+#define ED_PUTFILL(r,x)	(((r) & ~ED_FILL) | (((x) << ED_V_FILL) & ED_FILL))
+
 /* SCB offsets */
 
 #define SCB_MCHK	0x04				/* machine chk */
@@ -265,6 +319,7 @@
 #define SCB_TNV		0x24				/* TNV */
 #define SCB_TP		0x28				/* trace pending */
 #define SCB_BPT		0x2C				/* BPT instr */
+#define SCB_CMODE	0x30				/* comp mode fault */
 #define SCB_ARITH	0x34				/* arith fault */
 #define SCB_CHMK	0x40 				/* CHMK */
 #define SCB_CHME	0x44 				/* CHME */
@@ -458,10 +513,16 @@ enum opcodes {
  BBS, BBC, BBSS, BBCS, BBSC, BBCC, BBSSI, BBCCI,
  BLBS, BLBC, FFS, FFC, CMPV, CMPZV, EXTV, EXTZV,
  INSV, ACBL, AOBLSS, AOBLEQ, SOBGEQ, SOBGTR, CVTLB, CVTLW,
- ASHP, CVTLP, CALLG, CALLS, XFC, CVTGF = 0x133,
- ADDG2= 0x140, ADDG3, SUBG2, SUBG3, MULG2, MULG3, DIVG2, DIVG3,
+ ASHP, CVTLP, CALLG, CALLS, XFC, CVTDH = 0x132, CVTGF = 0x133,
+ ADDG2 = 0x140, ADDG3, SUBG2, SUBG3, MULG2, MULG3, DIVG2, DIVG3,
  CVTGB, CVTGW, CVTGL, CVTRGL, CVTBG, CVTWG, CVTLG, ACBG,
- MOVG, CMPG, MNEGG, TSTG, EMODG, POLYG, CVTFG = 0x199 };
+ MOVG, CMPG, MNEGG, TSTG, EMODG, POLYG, CVTGH,
+ ADDH2 = 0x160, ADDH3, SUBH2, SUBH3, MULH2, MULH3, DIVH2, DIVH3,
+ CVTHB, CVTHW, CVTHL, CVTRHL, CVTBH, CVTWH, CVTLH, ACBH,
+ MOVH, CMPH, MNEGH, TSTH, EMODH, POLYH, CVTHG,
+ CLRO = 0x176, MOVO, MOVAO, PUSHAO,
+ CVTFH = 0x198, CVTFG = 0x199,
+ CVTHF = 0x1F6, CVTHD = 0x1F7 };
 
 /* Repeated operations */
 
@@ -482,6 +543,7 @@ enum opcodes {
 #define BRANCHB(d)	PCQ_ENTRY, PC = PC + SXTB (d), FLUSH_ISTR
 #define BRANCHW(d)	PCQ_ENTRY, PC = PC + SXTW (d), FLUSH_ISTR
 #define JUMP(d)		PCQ_ENTRY, PC = (d), FLUSH_ISTR
+#define CMODE_JUMP(d)	PCQ_ENTRY, PC = (d)
 #define SETPC(d)	PC = (d), FLUSH_ISTR
 #define FLUSH_ISTR	ibcnt = 0, ppc = -1