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Bob Supnik's state as of 10/12/2013

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This commit is contained in:
Mark Pizzolato
2013-10-12 13:23:44 -07:00
parent 6031deddf8
commit 34ce1a038c
71 changed files with 5708 additions and 377 deletions
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62
PDP11/pdp11_rh.c
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@@ -1,6 +1,6 @@
/* pdp11_rh.c: PDP-11 Massbus adapter simulator
Copyright (c) 2005-2012, Robert M Supnik
Copyright (c) 2005-2013, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
rha, rhb RH11/RH70 Massbus adapter
02-Sep-13 RMS Added third Massbus adapter, debug printouts
19-Mar-12 RMS Fixed declaration of cpu_opt (Mark Pizzolato)
02-Feb-08 RMS Fixed DMA memory address limit test (John Dundas)
17-May-07 RMS Moved CS1 drive enable to devices
@@ -175,11 +176,12 @@ t_stat mba_set_type (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat mba_show_type (FILE *st, UNIT *uptr, int32 val, void *desc);
int32 mba0_inta (void);
int32 mba1_inta (void);
int32 mba2_inta (void);
void mba_set_int (uint32 mb);
void mba_clr_int (uint32 mb);
void mba_upd_cs1 (uint32 set, uint32 clr, uint32 mb);
void mba_set_cs2 (uint32 flg, uint32 mb);
uint32 mba_map_pa (int32 pa, int32 *ofs);
int32 mba_map_pa (int32 pa, int32 *ofs);
DEVICE mba0_dev, mba1_dev;
extern uint32 Map_Addr (uint32 ba);
@@ -272,6 +274,39 @@ MTAB mba1_mod[] = {
{ 0 }
};
DIB mba2_dib = {
IOBA_RS, IOLN_RS, &mba_rd, &mba_wr,
1, IVCL (RS), VEC_RS, { &mba2_inta }
};
UNIT mba2_unit = { UDATA (NULL, 0, 0) };
REG mba2_reg[] = {
{ ORDATA (CS1, massbus[2].cs1, 16) },
{ ORDATA (WC, massbus[2].wc, 16) },
{ ORDATA (BA, massbus[2].ba, 16) },
{ ORDATA (CS2, massbus[2].cs2, 16) },
{ ORDATA (DB, massbus[2].db, 16) },
{ ORDATA (BAE, massbus[2].bae, 6) },
{ ORDATA (CS3, massbus[2].cs3, 16) },
{ FLDATA (IFF, massbus[2].iff, 0) },
{ FLDATA (INT, IREQ (RS), INT_V_RS) },
{ FLDATA (SC, massbus[2].cs1, CSR_V_ERR) },
{ FLDATA (DONE, massbus[2].cs1, CSR_V_DONE) },
{ FLDATA (IE, massbus[2].cs1, CSR_V_IE) },
{ ORDATA (DEVADDR, mba2_dib.ba, 32), REG_HRO },
{ ORDATA (DEVVEC, mba2_dib.vec, 16), REG_HRO },
{ NULL }
};
MTAB mba2_mod[] = {
{ MTAB_XTD|MTAB_VDV, 0040, "ADDRESS", "ADDRESS",
&set_addr, &show_addr, NULL },
{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",
&set_vec, &show_vec, NULL },
{ 0 }
};
DEVICE mba_dev[] = {
{
"RHA", &mba0_unit, mba0_reg, mba0_mod,
@@ -286,6 +321,13 @@ DEVICE mba_dev[] = {
NULL, NULL, &mba_reset,
NULL, NULL, NULL,
&mba1_dib, DEV_DEBUG | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS
},
{
"RHC", &mba2_unit, mba2_reg, mba2_mod,
1, 0, 0, 0, 0, 0,
NULL, NULL, &mba_reset,
NULL, NULL, NULL,
&mba2_dib, DEV_DEBUG | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_QBUS
}
};
@@ -415,6 +457,9 @@ switch (ofs) { /* case on reg */
massbus[mb].cs1 &= ~(CS1_TRE | CS1_MCPE | CS1_DONE);
massbus[mb].cs2 &= ~CS2_ERR; /* clear errors */
massbus[mb].cs3 &= ~(CS3_ERR | CS3_DBL);
if (DEBUG_PRS (mba_dev[mb]))
fprintf (sim_deb, ">>RH%d STRT: cs1=%o, cs2=%o,ba=%o, wc=%o\n",
mb, massbus[mb].cs1, massbus[mb].cs2, massbus[mb].ba, massbus[mb].wc);
}
}
}
@@ -623,6 +668,9 @@ return i;
void mba_set_don (uint32 mb)
{
mba_upd_cs1 (CS1_DONE, 0, mb);
if (DEBUG_PRS (mba_dev[mb]))
fprintf (sim_deb, ">>RH%d DONE: cs1=%o, cs2=%o,ba=%o, wc=%o\n",
mb, massbus[mb].cs1, massbus[mb].cs2, massbus[mb].ba, massbus[mb].wc);
return;
}
@@ -726,9 +774,17 @@ massbus[1].iff = 0; /* clear CSTB INTR */
return mba1_dib.vec; /* acknowledge */
}
int32 mba2_inta (void)
{
massbus[2].cs1 &= ~CS1_IE; /* clear int enable */
massbus[2].cs3 &= ~CS1_IE; /* in both registers */
massbus[2].iff = 0; /* clear CSTB INTR */
return mba2_dib.vec; /* acknowledge */
}
/* Map physical address to Massbus number, offset */
uint32 mba_map_pa (int32 pa, int32 *ofs)
int32 mba_map_pa (int32 pa, int32 *ofs)
{
int32 i, uo, ba, lnt;
DIB *dibp;