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VAX: Added support for the DEQNA device on Ultrix 1.x. Henry Bent observed that the deqna driver in this OS counted on older DEQNA firmware which automatically enabled interrupts after a software reset.

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CPU Idle detection for this OS is now supported and the combination of SET CPU IDLE=ULTRIX-1.X and explicitly using a DEQNA device (SET XQ TYPE=DEQNA) will enable the automatic enabling of device interrupt generation.
This commit is contained in:
Mark Pizzolato
2014-07-14 12:29:53 -07:00
parent a0a7eb27b6
commit 4d817f1deb
4 changed files with 21 additions and 7 deletions
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7
PDP11/pdp11_xq.c
View File

@@ -2088,7 +2088,7 @@ void xqb_read_callback(int status)
void xq_sw_reset(CTLR* xq)
{
const uint16 set_bits = XQ_CSR_XL | XQ_CSR_RL;
uint16 set_bits = XQ_CSR_XL | XQ_CSR_RL;
int i;
sim_debug(DBG_TRC, xq->dev, "xq_sw_reset()\n");
@@ -2100,6 +2100,11 @@ void xq_sw_reset(CTLR* xq)
xq->var->iba = xq->var->srr = 0;
}
/* Old DEQNA firmware also enabled interrupts and */
/* the Ultrix 1.X driver counts on that behavior */
if ((xq->var->type == XQ_T_DEQNA) && xq->dib->vec && (ULTRIX1X))
set_bits |= XQ_CSR_IE;
/* reset csr bits */
xq_csr_set_clr(xq, set_bits, (uint16) ~set_bits);

4
PDP11/pdp11_xq.h
View File

@@ -75,12 +75,14 @@
extern int32 PSL; /* PSL */
extern int32 fault_PC; /* fault PC */
extern int32 int_req[IPL_HLVL];
uint32 cpu_idle_mask; /* idle mask (OS type) */
#define ULTRIX1X (cpu_idle_mask&VAX_IDLE_ULT1X)
#else /* PDP-11 version */
#include "pdp11_defs.h"
#define XQ_RDX 8
#define XQ_WID 16
extern int32 int_req[IPL_HLVL];
#define ULTRIX1X 0
#endif
#include "sim_ether.h"