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Notes For V3.0-0
Because some key files have changed, V3.0 should be unzipped to a clean directory. 1. New Features in 3.0-0 1.1 SCP and Libraries - Added ASSIGN/DEASSIGN (logical name) commands. - Changed RESTORE to unconditionally detach files. - Added E11 and TPC format support to magtape library. - Fixed bug in SHOW CONNECTIONS. - Added USE_ADDR64 support 1.2 All magtapes - Magtapes support SIMH format, E11 format, and TPC format (read only). - SET <tape_unit> FORMAT=format sets the specified tape unit's format. - SHOW <tape_unit> FORMAT displays the specified tape unit's format. - Tape format can also be set as part of the ATTACH command, using the -F switch. 1.3 VAX - VAX can be compiled without USE_INT64. - If compiled with USE_INT64 and USE_ADDR64, RQ and TQ controllers support files > 2GB. - VAX ROM has speed control (SET ROM DELAY/NODELAY). 2. Bugs Fixed in 3.01-0 2.1 VAX - Fixed CVTfi bug: integer overflow not set if exponent out of range - Fixed EMODx bugs: o First and second operands reversed o Separated fraction received wrong exponent o Overflow calculation on separated integer incorrect o Fraction not set to zero if exponent out of range - Fixed interval timer and ROM access to pass power-up self-test even on very fast host processors (fixes from Mark Pizzolato). 2.2 1401 - Fixed mnemonic, instruction lengths, and reverse scan length check bug for MCS. - Fixed MCE bug, BS off by 1 if zero suppress. - Fixed chaining bug, D lost if return to SCP. - Fixed H branch, branch occurs after continue. - Added check for invalid 8 character MCW, LCA. - Fixed magtape load-mode end of record response. 2.3 Nova - Fixed DSK variable size interaction with restore. 2.4 PDP-1 - Fixed DT variable size interaction with restore. 2.5 PDP-11 - Fixed DT variable size interaction with restore. - Fixed bug in MMR1 update (found by Tim Stark). - Added XQ features and fixed bugs: o Corrected XQ interrupts on IE state transition (code by Tom Evans). o Added XQ interrupt clear on soft reset. o Removed XQ interrupt when setting XL or RL (multiple people). o Added SET/SHOW XQ STATS. o Added SHOW XQ FILTERS. o Added ability to split received packet into multiple buffers. o Added explicit runt and giant packet processing. 2.6 PDP-18B - Fixed DT, RF variable size interaction with restore. - Fixed MT bug in MTTR. 2.7 PDP-8 - Fixed DT, DF, RF, RX variable size interaction with restore. - Fixed MT bug in SKTR. 2.8 HP2100 - Fixed bug in DP (13210A controller only), DQ read status. - Fixed bug in DP, DQ seek complete. 2.9 GRI - Fixed bug in SC queue pointer management. 3. New Features in 3.0 vs prior releases N/A 4. Bugs Fixed in 3.0 vs prior releases N/A 5. General Notes WARNING: The RESTORE command has changed. RESTORE will now detach an attached file on a unit, if that unit did not have an attached file in the saved configuration. This is required to assure that the unit flags and the file state are consistent. WARNING: The compilation scheme for the PDP-10, PDP-11, and VAX has changed. Use one of the supplied build files, or read the documentation carefully, before compiling any of these simulators.
This commit is contained in:
committed by
Mark Pizzolato
parent
43385c9616
commit
4ffd3be790
@@ -1,6 +1,6 @@
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/* gri_cpu.c: GRI-909 CPU simulator
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Copyright (c) 2001-2002, Robert M. Supnik
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Copyright (c) 2001-2003, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -23,6 +23,10 @@
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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cpu GRI-909 CPU
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14-Mar-03 RMS Fixed bug in SC queue tracking
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The system state for the GRI-909 is:
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AX<0:15> arithmetic input
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@@ -167,6 +171,7 @@ uint32 stop_opr = 1; /* stop ill operator */
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int16 scq[SCQ_SIZE] = { 0 }; /* PC queue */
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int32 scq_p = 0; /* PC queue ptr */
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REG *scq_r = NULL; /* PC queue reg ptr */
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extern int32 sim_interval;
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extern int32 sim_int_char;
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extern int32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
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@@ -340,7 +345,7 @@ REG cpu_reg[] = {
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{ FLDATA (ION, dev_done, INT_V_ON) },
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{ FLDATA (INODEF, dev_done, INT_V_NODEF) },
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{ FLDATA (BKP, bkp, 0) },
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{ BRDATA (SCQ, scq, 8, 15, SCQ_SIZE), REG_RO+REG_CIRC },
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{ BRDATA (SCQ, scq, 8, 15, SCQ_SIZE), REG_RO + REG_CIRC },
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{ ORDATA (SCQP, scq_p, 6), REG_HRO },
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{ FLDATA (STOP_OPR, stop_opr, 0) },
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{ ORDATA (WRU, sim_int_char, 8) },
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@@ -475,7 +480,7 @@ else if ((src != U_MEM) && (dst != U_MEM)) { /* reg-reg? */
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/* Memory reference. The second SC increment occurs after the first
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execution cycle. For direct, defer, and immediate defer, this is
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after the first memory read and before the bus transfer; but for
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immediate, it is before the bus transfer.
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immediate, it is after the bus transfer.
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*/
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else { SC = (SC + 1) & AMASK; /* incr SC */
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@@ -512,6 +517,7 @@ else { SC = (SC + 1) & AMASK; /* incr SC */
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/* Simulation halted */
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AO = ao_update (); /* update AO */
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scq_r->qptr = scq_p; /* update sc q ptr */
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return reason;
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}
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@@ -871,7 +877,7 @@ return SCPE_OK;
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t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)
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{
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int32 mc = 0;
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t_addr i;
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uint32 i;
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if ((val <= 0) || (val > MAXMEMSIZE) || ((val & 07777) != 0))
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return SCPE_ARG;
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