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Notes For V3.7-0
1. New Features 1.1 3.7-0 1.1.1 SCP - Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator execution rate and host resource utilization. - Added idle support (based on work by Mark Pizzolato). - Added -e to control error processing in nested DO commands (from Dave Bryan). 1.1.2 HP2100 - Added Double Integer instructions, 1000-F CPU, and Floating Point Processor (from Dave Bryan). - Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and 21xx binary loader protection (from Dave Bryan). 1.1.3 Interdata - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state. 1.1.4 PDP-11 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (WAIT instruction executed). - Added TA11/TU60 cassette support. 1.1.5 PDP-8 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). - Added TA8E/TU60 cassette support. 1.1.6 PDP-1 - Added support for 16-channel sequence break system. - Added support for PDP-1D extended features and timesharing clock. - Added support for Type 630 data communications subsystem. 1.1.6 PDP-4/7/9/15 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (keyboard poll loop or jump-to-self). 1.1.7 VAX, VAX780 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode). 1.1.8 PDP-10 - Added SET IDLE and SET NOIDLE commands to idle the simulator in wait state (operating system dependent). - Added CD20 (CD11) support. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
15919a2dd7
commit
53d02f7fa7
@@ -145,47 +145,55 @@
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/* Double precision operations on 64b quantities */
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#define F_LOAD(qd,ac,ds) ds.h = ac.h; ds.l = (qd)? ac.l: 0
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#define F_LOAD_P(qd,ac,ds) ds->h = ac.h; ds->l = (qd)? ac.l: 0
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#define F_LOAD_FRAC(qd,ac,ds) ds.h = (ac.h & FP_FRACH) | FP_HB; \
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ds.l = (qd)? ac.l: 0
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#define F_STORE(qd,sr,ac) ac.h = sr.h; if ((qd)) ac.l = sr.l
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#define F_STORE_P(qd,sr,ac) ac.h = sr->h; if ((qd)) ac.l = sr->l
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#define F_GET_FRAC_P(sr,ds) ds.l = sr->l; \
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ds.h = (sr->h & FP_FRACH) | FP_HB
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#define F_ADD(s2,s1,ds) ds.l = (s1.l + s2.l) & 0xFFFFFFFF; \
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ds.h = (s1.h + s2.h + (ds.l < s2.l)) & 0xFFFFFFFF
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#define F_SUB(s2,s1,ds) ds.h = (s1.h - s2.h - (s1.l < s2.l)) & 0xFFFFFFFF; \
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ds.l = (s1.l - s2.l) & 0xFFFFFFFF
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#define F_LT(x,y) ((x.h < y.h) || ((x.h == y.h) && (x.l < y.l)))
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#define F_LT_AP(x,y) (((x->h & ~FP_SIGN) < (y->h & ~FP_SIGN)) || \
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(((x->h & ~FP_SIGN) == (y->h & ~FP_SIGN)) && (x->l < y->l)))
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#define F_LOAD(qd,ac,ds) \
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ds.h = ac.h; ds.l = (qd)? ac.l: 0
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#define F_LOAD_P(qd,ac,ds) \
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ds->h = ac.h; ds->l = (qd)? ac.l: 0
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#define F_LOAD_FRAC(qd,ac,ds) \
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ds.h = (ac.h & FP_FRACH) | FP_HB; \
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ds.l = (qd)? ac.l: 0
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#define F_STORE(qd,sr,ac) \
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ac.h = sr.h; if ((qd)) ac.l = sr.l
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#define F_STORE_P(qd,sr,ac) \
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ac.h = sr->h; if ((qd)) ac.l = sr->l
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#define F_GET_FRAC_P(sr,ds) \
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ds.l = sr->l; \
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ds.h = (sr->h & FP_FRACH) | FP_HB
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#define F_ADD(s2,s1,ds) \
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ds.l = (s1.l + s2.l) & 0xFFFFFFFF; \
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ds.h = (s1.h + s2.h + (ds.l < s2.l)) & 0xFFFFFFFF
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#define F_SUB(s2,s1,ds) \
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ds.h = (s1.h - s2.h - (s1.l < s2.l)) & 0xFFFFFFFF; \
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ds.l = (s1.l - s2.l) & 0xFFFFFFFF
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#define F_LT(x,y) ((x.h < y.h) || ((x.h == y.h) && (x.l < y.l)))
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#define F_LT_AP(x,y) (((x->h & ~FP_SIGN) < (y->h & ~FP_SIGN)) || \
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(((x->h & ~FP_SIGN) == (y->h & ~FP_SIGN)) && (x->l < y->l)))
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#define F_LSH_V(sr,n,ds) \
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ds.h = (((n) >= 32)? (sr.l << ((n) - 32)): \
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(sr.h << (n)) | ((sr.l >> (32 - (n))) & and_mask[n])) \
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& 0xFFFFFFFF; \
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ds.l = ((n) >= 32)? 0: (sr.l << (n)) & 0xFFFFFFFF
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ds.h = (((n) >= 32)? (sr.l << ((n) - 32)): \
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(sr.h << (n)) | ((sr.l >> (32 - (n))) & and_mask[n])) \
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& 0xFFFFFFFF; \
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ds.l = ((n) >= 32)? 0: (sr.l << (n)) & 0xFFFFFFFF
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#define F_RSH_V(sr,n,ds) \
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ds.l = (((n) >= 32)? (sr.h >> ((n) - 32)) & and_mask[64 - (n)]: \
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((sr.l >> (n)) & and_mask[32 - (n)]) | \
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(sr.h << (32 - (n)))) & 0xFFFFFFFF; \
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ds.h = ((n) >= 32)? 0: \
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((sr.h >> (n)) & and_mask[32 - (n)]) & 0xFFFFFFFF
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ds.l = (((n) >= 32)? (sr.h >> ((n) - 32)) & and_mask[64 - (n)]: \
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((sr.l >> (n)) & and_mask[32 - (n)]) | \
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(sr.h << (32 - (n)))) & 0xFFFFFFFF; \
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ds.h = ((n) >= 32)? 0: \
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((sr.h >> (n)) & and_mask[32 - (n)]) & 0xFFFFFFFF
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/* For the constant shift macro, arguments must in the range [2,31] */
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#define F_LSH_1(ds) ds.h = ((ds.h << 1) | ((ds.l >> 31) & 1)) & 0xFFFFFFFF; \
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ds.l = (ds.l << 1) & 0xFFFFFFFF
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#define F_RSH_1(ds) ds.l = ((ds.l >> 1) & 0x7FFFFFFF) | ((ds.h & 1) << 31); \
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ds.h = ((ds.h >> 1) & 0x7FFFFFFF)
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#define F_LSH_1(ds) ds.h = ((ds.h << 1) | ((ds.l >> 31) & 1)) & 0xFFFFFFFF; \
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ds.l = (ds.l << 1) & 0xFFFFFFFF
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#define F_RSH_1(ds) ds.l = ((ds.l >> 1) & 0x7FFFFFFF) | ((ds.h & 1) << 31); \
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ds.h = ((ds.h >> 1) & 0x7FFFFFFF)
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#define F_LSH_K(sr,n,ds) \
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ds.h = ((sr.h << (n)) | ((sr.l >> (32 - (n))) & and_mask[n])) \
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& 0xFFFFFFFF; \
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ds.l = (sr.l << (n)) & 0xFFFFFFFF
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ds.h = ((sr.h << (n)) | ((sr.l >> (32 - (n))) & and_mask[n])) \
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& 0xFFFFFFFF; \
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ds.l = (sr.l << (n)) & 0xFFFFFFFF
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#define F_RSH_K(sr,n,ds) \
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ds.l = (((sr.l >> (n)) & and_mask[32 - (n)]) | \
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(sr.h << (32 - (n)))) & 0xFFFFFFFF; \
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ds.h = ((sr.h >> (n)) & and_mask[32 - (n)]) & 0xFFFFFFFF
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ds.l = (((sr.l >> (n)) & and_mask[32 - (n)]) | \
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(sr.h << (32 - (n)))) & 0xFFFFFFFF; \
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ds.h = ((sr.h >> (n)) & and_mask[32 - (n)]) & 0xFFFFFFFF
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#define F_LSH_GUARD(ds) F_LSH_K(ds,FP_GUARD,ds)
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#define F_RSH_GUARD(ds) F_RSH_K(ds,FP_GUARD,ds)
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@@ -252,7 +260,8 @@ int32 i, qdouble, lenf, leni;
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int32 newV, exp, sign;
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fpac_t fac, fsrc, modfrac;
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static const uint32 i_limit[2][2] = {
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{ 0x80000000, 0x80010000 }, { 0x80000000, 0x80000001 }
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{ 0x80000000, 0x80010000 },
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{ 0x80000000, 0x80000001 }
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};
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backup_PC = PC; /* save PC for FEA */
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@@ -433,7 +442,7 @@ switch ((IR >> 8) & 017) { /* decode IR<11:8> */
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if (FPS & FPS_L) {
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leni = LONG;
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i = FP_BIAS + 32;
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}
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}
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else {
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leni = WORD;
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i = FP_BIAS + 16;
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@@ -602,7 +611,8 @@ return 0;
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uint32 ReadI (int32 VA, int32 spec, int32 len)
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{
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if ((len == WORD) || (spec == 027)) return (ReadW (VA) << 16);
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return ((ReadW (VA) << 16) | ReadW ((VA & ~0177777) | ((VA + 2) & 0177777)));
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return ((ReadW (VA) << 16) |
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ReadW ((VA & ~0177777) | ((VA + 2) & 0177777)));
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}
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/* Read floating operand
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