github.com/open-simh.simh
1
0
Fork 0
mirror of https://github.com/open-simh/simh.git synced 2026-02-18 05:34:55 +00:00
Code Issues Projects Releases Wiki Activity

Notes For V3.7-0

Browse Source 
1. New Features

1.1 3.7-0

1.1.1 SCP

- Added SET THROTTLE and SET NOTHROTTLE commands to regulate simulator
  execution rate and host resource utilization.
- Added idle support (based on work by Mark Pizzolato).
- Added -e to control error processing in nested DO commands (from
  Dave Bryan).

1.1.2 HP2100

- Added Double Integer instructions, 1000-F CPU, and Floating Point
  Processor (from Dave Bryan).
- Added 2114 and 2115 CPUs, 12607B and 12578A DMA controllers, and
  21xx binary loader protection (from Dave Bryan).

1.1.3 Interdata

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state.

1.1.4 PDP-11

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (WAIT instruction executed).
- Added TA11/TU60 cassette support.

1.1.5 PDP-8

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (keyboard poll loop or jump-to-self).
- Added TA8E/TU60 cassette support.

1.1.6 PDP-1

- Added support for 16-channel sequence break system.
- Added support for PDP-1D extended features and timesharing clock.
- Added support for Type 630 data communications subsystem.

1.1.6 PDP-4/7/9/15

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (keyboard poll loop or jump-to-self).

1.1.7 VAX, VAX780

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (more than 200 cycles at IPL's 0, 1, or 3 in kernel mode).

1.1.8 PDP-10

- Added SET IDLE and SET NOIDLE commands to idle the simulator in wait
  state (operating system dependent).
- Added CD20 (CD11) support.

2. Bugs Fixed

Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
2007-02-03 14:59:00 -08:00
committed by Mark Pizzolato
parent 15919a2dd7
commit 53d02f7fa7
161 changed files with 18604 additions and 6903 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
VAX/vax780_defs.h
View File

@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
29-Oct-2006 RMS Added clock coscheduler function
17-May-2006 RMS Added CR11/CD11 support (from John Dundas)
10-May-2006 RMS Added model-specific reserved operand check macros
@@ -418,5 +419,6 @@ t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
void sbi_set_errcnf (void);
int32 clk_cosched (int32 wait);
#endif

26
VAX/vax780_stddev.c
View File

@@ -29,6 +29,8 @@
todr TODR clock
tmr interval timer
29-Oct-2006 RMS Added clock coscheduler function
Synced keyboard to clock for idling
11-May-06 RMS Revised timer logic for EVKAE
22-Nov-05 RMS Revised for new terminal processing routines
10-Mar-05 RMS Fixed bug in timer schedule routine (from Mark Hittinger)
@@ -102,7 +104,7 @@
#define TMR_CSR_WR (TMR_CSR_IE | TMR_CSR_RUN)
#define TMR_INC 10000 /* usec/interval */
#define CLK_DELAY 5000 /* 100 Hz */
#define TMXR_MULT 2 /* 50 Hz */
#define TMXR_MULT 1 /* 100 Hz */
/* Floppy definitions */
@@ -210,7 +212,7 @@ void fl_protocol_error (void);
tti_reg TTI register list
*/
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), KBD_POLL_WAIT };
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (RXDB, tti_buf, 16) },
@@ -219,7 +221,7 @@ REG tti_reg[] = {
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
@@ -253,7 +255,7 @@ REG tto_reg[] = {
{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
{ FLDATA (IE, tto_csr, CSR_V_IE) },
{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT + REG_NZ },
{ NULL }
};
@@ -416,7 +418,7 @@ t_stat tti_svc (UNIT *uptr)
{
int32 c;
sim_activate (uptr, uptr->wait); /* continue poll */
sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
if (c & SCPE_BREAK) /* break? */
tti_buf = RXDB_ERR | RXDB_FRM;
@@ -434,7 +436,7 @@ t_stat tti_reset (DEVICE *dptr)
tti_buf = 0;
tti_csr = 0;
tti_int = 0;
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
return SCPE_OK;
}
@@ -613,12 +615,22 @@ else tmr_use_100hz = 1; /* let clk handle */
return;
}
/* Clock coscheduling routine */
int32 clk_cosched (int32 wait)
{
int32 t;
t = sim_is_active (&clk_unit);
return (t? t - 1: wait);
}
/* 100Hz clock reset */
t_stat clk_reset (DEVICE *dptr)
{
tmr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init 100Hz timer */
sim_activate (&clk_unit, tmr_poll); /* activate 100Hz unit */
sim_activate_abs (&clk_unit, tmr_poll); /* activate 100Hz unit */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}

17
VAX/vax_cis.c
View File

@@ -1219,10 +1219,12 @@ return TestDstr (src); /* clean -0 */
(to allow for external overflow calculations)
The rules for the stored sign and the PSW sign are:
- Stored sign is negative if input is negative, and the result
is non-zero or there was overflow
- PSL sign is negative if input is negative, and the result is
non-zero
- Stored sign is negative if input is negative, and the result
is non-zero or there was overflow
- PSL sign is negative if input is negative, and the result is
non-zero
Thus, the stored sign and the PSL sign will differ in one case:
a negative zero generated by overflow is stored with a negative
sign, but PSL.N is clear
@@ -1297,16 +1299,18 @@ return;
cy = carry in
Output = 1 if carry, 0 if no carry
This algorithm courtesy Anton Chernoff, circa 1992 or even earlier
This algorithm courtesy Anton Chernoff, circa 1992 or even earlier.
We trace the history of a pair of adjacent digits to see how the
carry is fixed; each parenthesized item is a 4b digit.
Assume we are adding:
(a)(b) I
+ (x)(y) J
First compute I^J:
(a^x)(b^y) TMP
Note that the low bit of each digit is the same as the low bit of
@@ -1315,6 +1319,7 @@ return;
Now compute I+J+66 to get decimal addition with carry forced left
one digit:
(a+x+6+carry mod 16)(b+y+6 mod 16) SUM
Note that if there was a carry from b+y+6, then the low bit of the
@@ -1429,7 +1434,7 @@ return ((nz - 1) * 8) + i;
mtable[10] = array of decimal string structures
Note that dsrc has a high order zero nibble; this
guarantees that the largest multiple won't overflow
guarantees that the largest multiple won't overflow
Also note that mtable[0] is not filled in
*/

47
VAX/vax_cpu.c
View File

@@ -25,6 +25,7 @@
cpu VAX central processor
29-Oct-06 RMS Added idle support
22-May-06 RMS Fixed format error in CPU history (found by Peter Schorn)
10-May-06 RMS Added -kesu switches for virtual addressing modes
Fixed bugs in examine virtual
@@ -245,6 +246,8 @@ int32 cpu_astop = 0;
int32 mchk_va, mchk_ref; /* mem ref param */
int32 ibufl, ibufh; /* prefetch buf */
int32 ibcnt, ppc; /* prefetch ctl */
uint32 cpu_idle_ipl_mask = 0xB; /* idle if on IPL 0,1,3 */
int32 cpu_idle_wait = 200; /* for this many cycles */
jmp_buf save_env;
REG *pcq_r = NULL; /* PC queue reg ptr */
int32 pcq[PCQ_SIZE] = { 0 }; /* PC queue */
@@ -280,6 +283,7 @@ extern int32 sim_interval;
extern int32 sim_int_char;
extern int32 sim_switches;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
extern UNIT clk_unit;
extern t_stat build_dib_tab (void);
@@ -371,6 +375,8 @@ int32 cpu_get_vsw (int32 sw);
int32 get_istr (int32 lnt, int32 acc);
int32 ReadOcta (int32 va, int32 *opnd, int32 j, int32 acc);
t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line);
int32 cpu_psl_ipl (int32 newpsl);
t_stat cpu_idle_svc (UNIT *uptr);
/* CPU data structures
@@ -380,7 +386,9 @@ t_bool cpu_show_opnd (FILE *st, InstHistory *h, int32 line);
cpu_mod CPU modifier list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, INITMEMSIZE) };
UNIT cpu_unit = {
UDATA (&cpu_idle_svc, UNIT_FIX|UNIT_BINK, INITMEMSIZE)
};
REG cpu_reg[] = {
{ HRDATA (PC, R[nPC], 32) },
@@ -425,6 +433,8 @@ REG cpu_reg[] = {
{ FLDATA (CRDERR, crd_err, 0) },
{ FLDATA (MEMERR, mem_err, 0) },
{ FLDATA (HLTPIN, hlt_pin, 0) },
{ HRDATA (IDLE_IPL, cpu_idle_ipl_mask, 16), REG_HIDDEN },
{ DRDATA (IDLE_WAIT, cpu_idle_wait, 16), REG_HIDDEN },
{ BRDATA (PCQ, pcq, 16, 32, PCQ_SIZE), REG_RO+REG_CIRC },
{ HRDATA (PCQP, pcq_p, 6), REG_HRO },
{ HRDATA (BADABO, badabo, 32), REG_HRO },
@@ -433,6 +443,10 @@ REG cpu_reg[] = {
};
MTAB cpu_mod[] = {
{ UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL },
{ UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL },
{ MTAB_XTD|MTAB_VDV, 0, "IDLE", "IDLE", &sim_set_idle, &sim_show_idle },
{ MTAB_XTD|MTAB_VDV, 0, NULL, "NOIDLE", &sim_clr_idle, NULL },
{ UNIT_MSIZE, (1u << 23), NULL, "8M", &cpu_set_size },
{ UNIT_MSIZE, (1u << 24), NULL, "16M", &cpu_set_size },
{ UNIT_MSIZE, (1u << 25), NULL, "32M", &cpu_set_size },
@@ -443,8 +457,6 @@ MTAB cpu_mod[] = {
{ UNIT_MSIZE, (1u << 28), NULL, "256M", &cpu_set_size },
{ UNIT_MSIZE, (1u << 29), NULL, "512M", &cpu_set_size },
#endif
{ UNIT_CONH, 0, "HALT to SIMH", "SIMHALT", NULL },
{ UNIT_CONH, UNIT_CONH, "HALT to console", "CONHALT", NULL },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
&cpu_set_hist, &cpu_show_hist },
{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "VIRTUAL", NULL,
@@ -1515,8 +1527,7 @@ for ( ;; ) {
/* Single operand instructions with source, read only - TSTx src.rx
opnd[0] = source
*/
*/
case TSTB:
CC_IIZZ_B (op0); /* set cc's */
@@ -2943,6 +2954,30 @@ opnd[j++] = Read (va + 12, L_LONG, acc);
return j;
}
/* Set new PSL IPL */
int32 cpu_psl_ipl (int32 newpsl)
{
if (((newpsl ^ PSL) & PSL_IPL) != 0) {
sim_cancel (&cpu_unit);
if (sim_idle_enab && ((newpsl & PSL_CUR) == 0)) {
uint32 newipl = PSL_GETIPL (newpsl);
if (cpu_idle_ipl_mask & (1u << newipl))
sim_activate (&cpu_unit, cpu_idle_wait);
}
}
return newpsl;
}
/* Idle timer has expired with no PSL change */
t_stat cpu_idle_svc (UNIT *uptr)
{
if (sim_idle_enab)
sim_idle (TMR_CLK, FALSE);
return SCPE_OK;
}
/* Reset */
t_stat cpu_reset (DEVICE *dptr)
@@ -2950,7 +2985,7 @@ t_stat cpu_reset (DEVICE *dptr)
hlt_pin = 0;
mem_err = 0;
crd_err = 0;
PSL = PSL_IS | PSL_IPL1F;
PSL = cpu_psl_ipl (PSL_IS | PSL_IPL1F);
SISR = 0;
ASTLVL = 4;
mapen = 0;

17
VAX/vax_cpu1.c
View File

@@ -111,6 +111,8 @@ extern t_bool chk_tb_ent (uint32 va);
extern int32 ReadIPR (int32 rg);
extern void WriteIPR (int32 rg, int32 val);
extern t_bool BadCmPSL (int32 newpsl);
extern int32 cpu_psl_ipl (int32 newpsl);
extern jmp_buf save_env;
/* Branch on bit and no modify
@@ -1079,9 +1081,9 @@ else {
SP = KSP; /* new stack */
}
}
if (ei > 0) PSL = newpsl | (ipl << PSL_V_IPL); /* if int, new IPL */
else PSL = newpsl | ((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) |
(oldcur << PSL_V_PRV);
if (ei > 0) PSL = cpu_psl_ipl (newpsl | (ipl << PSL_V_IPL)); /* if int, new IPL */
else PSL = cpu_psl_ipl (newpsl |
((newpc & 1)? PSL_IPL1F: (oldpsl & PSL_IPL)) | (oldcur << PSL_V_PRV));
if (DEBUG_PRI (cpu_dev, LOG_CPU_I)) fprintf (sim_deb,
">>IEX: PC=%08x, PSL=%08x, SP=%08x, VEC=%08x, nPSL=%08x, nSP=%08x\n",
PC, oldpsl, oldsp, vec, PSL, SP);
@@ -1124,7 +1126,7 @@ Write (tsp - 8, PC, L_LONG, WA); /* push PC */
Write (tsp - 4, PSL | cc, L_LONG, WA); /* push PSL */
SP = tsp - 12; /* set new stk */
PSL = (mode << PSL_V_CUR) | (PSL & PSL_IPL) | /* set new PSL */
(cur << PSL_V_PRV);
(cur << PSL_V_PRV); /* IPL unchanged */
last_chm = fault_PC;
JUMP (newpc & ~03); /* set new PC */
return 0; /* cc = 0 */
@@ -1184,7 +1186,7 @@ else STK[oldcur] = SP;
if (DEBUG_PRI (cpu_dev, LOG_CPU_R)) fprintf (sim_deb,
">>REI: PC=%08x, PSL=%08x, SP=%08x, nPC=%08x, nPSL=%08x, nSP=%08x\n",
PC, PSL, SP - 8, newpc, newpsl, ((newpsl & IS)? IS: STK[newcur]));
PSL = (PSL & PSL_TP) | (newpsl & ~CC_MASK); /* set new PSL */
PSL = cpu_psl_ipl ((PSL & PSL_TP) | (newpsl & ~CC_MASK)); /* set new PSL */
if (PSL & PSL_IS) SP = IS; /* set new stack */
else {
SP = STK[newcur]; /* if ~IS, chk AST */
@@ -1275,7 +1277,8 @@ if (PSL & PSL_IS) SP = SP + 8; /* int stack? */
else {
KSP = SP + 8; /* pop kernel stack */
SP = IS; /* switch to int stk */
if ((PSL & PSL_IPL) == 0) PSL = PSL | PSL_IPL1; /* make IPL > 0 */
if ((PSL & PSL_IPL) == 0) /* make IPL > 0 */
PSL = cpu_psl_ipl (PSL | PSL_IPL1);
PSL = PSL | PSL_IS; /* set PSL<is> */
}
pcbpa = PCBB & PAMASK;
@@ -1436,7 +1439,7 @@ switch (prn) { /* case on reg # */
break;
case MT_IPL: /* IPL */
PSL = (PSL & ~PSL_IPL) | ((val & PSL_M_IPL) << PSL_V_IPL);
PSL = cpu_psl_ipl ((PSL & ~PSL_IPL) | ((val & PSL_M_IPL) << PSL_V_IPL));
break;
case MT_ASTLVL: /* ASTLVL */

29
VAX/vax_stddev.c
View File

@@ -1,6 +1,6 @@
/* vax_stddev.c: VAX 3900 standard I/O devices
Copyright (c) 1998-2005, Robert M Supnik
Copyright (c) 1998-2006, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -27,6 +27,7 @@
tto terminal output
clk 100Hz and TODR clock
17-Oct-06 RMS Synced keyboard poll to real-time clock for idling
22-Nov-05 RMS Revised for new terminal processing routines
09-Sep-04 RMS Integrated powerup into RESET (with -p)
28-May-04 RMS Removed SET TTI CTRL-C
@@ -54,7 +55,7 @@
#define CLKCSR_IMP (CSR_IE) /* real-time clock */
#define CLKCSR_RW (CSR_IE)
#define CLK_DELAY 5000 /* 100 Hz */
#define TMXR_MULT 2 /* 50 Hz */
#define TMXR_MULT 1 /* 100 Hz */
extern int32 int_req[IPL_HLVL];
extern int32 hlt_pin;
@@ -87,7 +88,7 @@ extern int32 sysd_hlt_enb (void);
DIB tti_dib = { 0, 0, NULL, NULL, 1, IVCL (TTI), SCB_TTI, { NULL } };
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), KBD_POLL_WAIT };
UNIT tti_unit = { UDATA (&tti_svc, TT_MODE_8B, 0), 0 };
REG tti_reg[] = {
{ HRDATA (BUF, tti_unit.buf, 16) },
@@ -96,7 +97,7 @@ REG tti_reg[] = {
{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
{ FLDATA (IE, tti_csr, CSR_V_IE) },
{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
{ DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },
{ NULL }
};
@@ -281,7 +282,7 @@ t_stat tti_svc (UNIT *uptr)
{
int32 c;
sim_activate (uptr, uptr->wait); /* continue poll */
sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
if (c & SCPE_BREAK) { /* break? */
if (sysd_hlt_enb ()) hlt_pin = 1; /* if enabled, halt */
@@ -299,7 +300,7 @@ t_stat tti_reset (DEVICE *dptr)
tti_unit.buf = 0;
tti_csr = 0;
CLR_INT (TTI);
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));
return SCPE_OK;
}
@@ -356,6 +357,18 @@ if (!todr_blow) todr_reg = todr_reg + 1; /* incr TODR */
return SCPE_OK;
}
/* Clock coscheduling routine */
int32 clk_cosched (int32 wait)
{
int32 t;
t = sim_is_active (&clk_unit);
return (t? t - 1: wait);
}
/* Powerup routine */
t_stat todr_powerup (void)
{
uint32 base;
@@ -375,6 +388,8 @@ todr_blow = 0;
return SCPE_OK;
}
/* Reset routine */
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
@@ -383,7 +398,7 @@ if (sim_switches & SWMASK ('P')) todr_powerup (); /* powerup? */
clk_csr = 0;
CLR_INT (CLK);
t = sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init timer */
sim_activate (&clk_unit, t); /* activate unit */
sim_activate_abs (&clk_unit, t); /* activate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
return SCPE_OK;

28
VAX/vax_syscm.c
View File

@@ -1,6 +1,6 @@
/* vax_syscm.c: PDP-11 compatibility mode symbolic decode and parse
Copyright (c) 1993-2005, Robert M Supnik
Copyright (c) 1993-2006, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,7 +23,8 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
27-Sep-05 RMS Fixed warnings compiling with 64b addresses
12-Nov-06 RMS Fixed operand order in EIS instructions (found by W.F.J. Mueller)
27-Sep-05 RMS Fixed warnings compiling with 64b addresses
15-Sep-04 RMS Cloned from pdp11_sys.c
*/
@@ -49,6 +50,7 @@ extern UNIT cpu_unit;
#define I_V_DOP 9 /* double operand */
#define I_V_CCC 10 /* CC clear */
#define I_V_CCS 11 /* CC set */
#define I_V_SOPR 12 /* operand, reg */
#define I_NPN (I_V_NPN << I_V_CL)
#define I_REG (I_V_REG << I_V_CL)
#define I_SOP (I_V_SOP << I_V_CL)
@@ -61,11 +63,13 @@ extern UNIT cpu_unit;
#define I_DOP (I_V_DOP << I_V_CL)
#define I_CCC (I_V_CCC << I_V_CL)
#define I_CCS (I_V_CCS << I_V_CL)
#define I_SOPR (I_V_SOPR << I_V_CL)
static const int32 masks[] = {
0177777, 0177770, 0177700, 0177770,
0177000, 0177400, 0177700, 0177000,
0177400, 0170000, 0177777, 0177777
0177400, 0170000, 0177777, 0177777,
0177000
};
static const char *opcode[] = {
@@ -145,7 +149,7 @@ static const int32 opc_val[] = {
0007000+I_SOP, 0007200+I_SOP, 0007300+I_SOP,
0010000+I_DOP, 0020000+I_DOP, 0030000+I_DOP, 0040000+I_DOP,
0050000+I_DOP, 0060000+I_DOP,
0070000+I_RSOP, 0071000+I_RSOP, 0072000+I_RSOP, 0073000+I_RSOP,
0070000+I_SOPR, 0071000+I_SOPR, 0072000+I_SOPR, 0073000+I_SOPR,
0074000+I_RSOP,
0075000+I_REG, 0075010+I_REG, 0075020+I_REG, 0075030+I_REG,
0076020+I_REG,
@@ -335,6 +339,12 @@ for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */
wd1 = fprint_spec (of, addr, dstm, val[1]);
break;
case I_V_SOPR: /* sopr */
fprintf (of, "%s ", opcode[i]);
wd1 = fprint_spec (of, addr, dstm, val[1]);
fprintf (of, ",%s", rname[srcr]);
break;
case I_V_DOP: /* dop */
fprintf (of, "%s ", opcode[i]);
wd1 = fprint_spec (of, addr, srcm, val[1]);
@@ -609,6 +619,16 @@ switch (j) { /* case on class */
val[0] = val[0] | spec;
break;
case I_V_SOPR: /* dop, reg */
cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
if ((n1 = get_spec (gbuf, ad32, 0, &spec, &val[1])) > 0)
return SCPE_ARG;
val[0] = val[0] | spec;
cptr = get_glyph (cptr, gbuf, 0); /* get glyph */
if ((reg = get_reg (gbuf, 0)) < 0) return SCPE_ARG;
val[0] = val[0] | (reg << 6);
break;
case I_V_DOP: /* double op */
cptr = get_glyph (cptr, gbuf, ','); /* get glyph */
if ((n1 = get_spec (gbuf, ad32, 0, &spec, &val[1])) > 0)

16
VAX/vax_sysdev.c
View File

@@ -85,7 +85,7 @@
#define CMERR_BUS 0x00000080 /* bus err NI */
#define CMERR_SYN 0x0000007F /* syndrome NI */
#define CMERR_W1C (CMERR_RDS | CMERR_FRQ | CMERR_CRD | \
CMERR_DMA | CMERR_BUS)
CMERR_DMA | CMERR_BUS)
/* CMCTL control/status register */
@@ -97,7 +97,7 @@
#define CMCSR_DCM 0x00000080 /* diag mode NI */
#define CMCSR_SYN 0x0000007F /* syndrome NI */
#define CMCSR_MASK (CMCSR_PMI | CMCSR_CRD | CMCSR_DET | \
CMCSR_FDT | CMCSR_DCM | CMCSR_SYN)
CMCSR_FDT | CMCSR_DCM | CMCSR_SYN)
/* KA655 boot/diagnostic register */
@@ -276,6 +276,7 @@ extern void txcs_wr (int32 dat);
extern void txdb_wr (int32 dat);
extern void ioreset_wr (int32 dat);
extern uint32 sim_os_msec();
extern int32 cpu_psl_ipl (int32 newpsl);
/* ROM data structures
@@ -901,7 +902,7 @@ struct reglink { /* register linkage */
uint32 low; /* low addr */
uint32 high; /* high addr */
t_stat (*read)(int32 pa); /* read routine */
void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */
void (*write)(int32 pa, int32 val, int32 lnt); /* write routine */
};
struct reglink regtable[] = {
@@ -1047,10 +1048,10 @@ int32 rg = (pa - KABASE) >> 2;
switch (rg) {
case 0: /* CACR */
case 0: /* CACR */
return ka_cacr;
case 1: /* BDR */
case 1: /* BDR */
return ka_bdr;
}
@@ -1500,7 +1501,7 @@ else STK[temp] = SP; /* save stack */
if (mapen) conpsl = conpsl | CON_MAPON; /* mapping on? */
mapen = 0; /* turn off map */
SP = IS; /* set SP from IS */
PSL = PSL_IS | PSL_IPL1F; /* PSL = 41F0000 */
PSL = cpu_psl_ipl (PSL_IS | PSL_IPL1F); /* PSL = 41F0000 */
JUMP (ROMBASE); /* PC = 20040000 */
return 0; /* new cc = 0 */
}
@@ -1514,7 +1515,7 @@ extern FILE *sim_log;
t_stat r;
PC = ROMBASE;
PSL = PSL_IS | PSL_IPL1F;
PSL = cpu_psl_ipl (PSL_IS | PSL_IPL1F);
conpc = 0;
conpsl = PSL_IS | PSL_IPL1F | CON_PWRUP;
if (rom == NULL) return SCPE_IERR;
@@ -1569,4 +1570,3 @@ ssc_bto = 0;
ssc_otp = 0;
return SCPE_OK;
}

3
VAX/vax_syslist.c
View File

@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
17-Oct-06 RMS Re-ordered device list
17-May-06 RMS Added CR11/CD11 support (from John Dundas)
01-Oct-2004 RMS Cloned from vax_sys.c
*/
@@ -63,11 +64,11 @@ DEVICE *sim_devices[] = {
&nvr_dev,
&sysd_dev,
&qba_dev,
&clk_dev,
&tti_dev,
&tto_dev,
&csi_dev,
&cso_dev,
&clk_dev,
&dz_dev,
&vh_dev,
&cr_dev,

2
VAX/vaxmod_defs.h
View File

@@ -453,4 +453,6 @@ t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);
t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
t_stat auto_config (char *name, int32 num);
int32 clk_cosched (int32 wait);
#endif