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Notes For V3.8

Browse Source 
The makefile now works for Linux and most Unix's. Howevr, for Solaris
and MacOS, you must first export the OSTYPE environment variable:

> export OSTYPE
> make

Otherwise, you will get build errors.

1. New Features

1.1 3.8-0

1.1.1 SCP and Libraries

- BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and
  show (respectively) a breakpoint at the current PC.

1.2 GRI

- Added support for the GRI-99 processor.

1.3 HP2100

- Added support for the BACI terminal interface.
- Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions.

1.4 Nova

- Added support for 64KW memory (implemented in third-party CPU's).

1.5 PDP-11

- Added support for DC11, RC11, KE11A, KG11A.
- Added modem control support for DL11.
- Added ASCII character support for all 8b devices.

2. Bugs Fixed

Please see the revision history on http://simh.trailing-edge.com or
in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
2008-06-24 14:21:00 -07:00
committed by Mark Pizzolato
parent 3cb7c60d5d
commit 59aa4a73b1
136 changed files with 57039 additions and 10915 deletions
Download Patch File Download Diff File Expand all files Collapse all files

217
GRI/gri_cpu.c
View File

@@ -1,6 +1,6 @@
/* gri_cpu.c: GRI-909 CPU simulator
Copyright (c) 2001-2007, Robert M. Supnik
Copyright (c) 2001-2008, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,24 +23,26 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
cpu GRI-909 CPU
cpu GRI-909/GRI-99 CPU
14-Jan-08 RMS Added GRI-99 support
28-Apr-07 RMS Removed clock initialization
22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
18-Jul-04 RMS Fixed missing ao_update calls in AX, AY write
17-Jul-04 RMS Revised MSR, EAO based on additional documentation
14-Mar-03 RMS Fixed bug in SC queue tracking
The system state for the GRI-909 is:
The system state for the GRI-909/GRI-99 is:
AX<0:15> arithmetic input
AY<0:15> arithmetic input
BSW<0:15> byte swapper
BPK<0:15> byte packer
GR[0:5]<0:15> extended general registers
MSR<0:15> machine status register
TRP<0:15> trap register (subroutine return)
SC<0:14> sequence counter
AX<15:0> arithmetic input
AY<15:0> arithmetic input
BSW<15:0> byte swapper
BPK<15:0> byte packer
GR[0:5]<15:0> extended general registers
MSR<15:0> machine status register
TRP<15:0> trap register (subroutine return)
SC<14:0> sequence counter
XR<15:0> index register (GRI-99 only)
The GRI-909 has, nominally, just one instruction format: move.
@@ -149,10 +151,20 @@
#define SCQ_SIZE 64 /* must be 2**n */
#define SCQ_MASK (SCQ_SIZE - 1)
#define SCQ_ENTRY scq[scq_p = (scq_p - 1) & SCQ_MASK] = SC
#define UNIT_V_NOEAO (UNIT_V_UF) /* EAO absent */
#define UNIT_NOEAO (1 << UNIT_V_NOEAO)
#define UNIT_V_MSIZE (UNIT_V_UF + 1) /* dummy mask */
#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
#define UNIT_V_AO (UNIT_V_UF + 0) /* AO */
#define UNIT_AO (1u << UNIT_V_AO)
#define UNIT_V_EAO (UNIT_V_UF + 1) /* EAO */
#define UNIT_EAO (1u << UNIT_V_EAO)
#define UNIT_V_GPR (UNIT_V_UF + 2) /* GPR */
#define UNIT_GPR (1u << UNIT_V_GPR)
#define UNIT_V_BSWPK (UNIT_V_UF + 3) /* BSW-BPK */
#define UNIT_BSWPK (1u << UNIT_V_BSWPK)
#define UNIT_V_GRI99 (UNIT_V_UF + 4) /* GRI-99 */
#define UNIT_GRI99 (1u << UNIT_V_GRI99)
#define UNIT_V_MSIZE (UNIT_V_UF + 5) /* dummy mask */
#define UNIT_MSIZE (1u << UNIT_V_MSIZE)
#define IDX_ADD(x) ((((cpu_unit.flags & UNIT_GRI99) && ((x) & INDEX))? ((x) + XR): (x)) & AMASK)
uint16 M[MAXMEMSIZE] = { 0 }; /* memory */
uint32 SC; /* sequence cntr */
@@ -166,6 +178,7 @@ uint32 BSW, BPK; /* byte swap, pack */
uint32 GR[6]; /* extended general regs */
uint32 SWR; /* switch reg */
uint32 DR; /* display register */
uint32 XR; /* index register */
uint32 thwh = 0; /* thumbwheel */
uint32 dev_done = 0; /* device flags */
uint32 bkp = 0; /* bkpt pending */
@@ -197,6 +210,9 @@ uint32 zero_sf (uint32 op);
uint32 ir_rd (uint32 op);
t_stat ir_fo (uint32 op);
uint32 trp_rd (uint32 src);
t_stat trp_wr (uint32 dst, uint32 val);
uint32 atrp_rd (uint32 src);
t_stat atrp_wr (uint32 dst, uint32 val);
uint32 isr_rd (uint32 src);
t_stat isr_wr (uint32 dst, uint32 val);
t_stat isr_fo (uint32 op);
@@ -224,6 +240,8 @@ uint32 bpk_rd (uint32 src);
t_stat bpk_wr (uint32 dst, uint32 val);
uint32 gr_rd (uint32 src);
t_stat gr_wr (uint32 dst, uint32 val);
uint32 xr_rd (uint32 src);
t_stat xr_wr (uint32 dst, uint32 val);
extern t_stat rtc_fo (uint32 op);
extern uint32 rtc_sf (uint32 op);
@@ -240,9 +258,9 @@ struct gdev dev_tab[64] = {
{ &zero_rd, &zero_wr, &zero_fo, &zero_sf }, /* 00: zero */
{ &ir_rd, &zero_wr, &ir_fo, &zero_sf }, /* ir */
{ &no_rd, &no_wr, &no_fo, &no_sf }, /* fo/sf */
{ &trp_rd, &no_wr, &zero_fo, &zero_sf }, /* trp */
{ &trp_rd, &trp_wr, &zero_fo, &zero_sf }, /* trp */
{ &isr_rd, &isr_wr, &isr_fo, &isr_sf }, /* isr */
{ &ma_rd, &no_wr, &no_fo, &no_sf }, /* MA */
{ &ma_rd, &no_wr, &no_fo, &no_sf }, /* ma */
{ &mem_rd, &mem_wr, &zero_fo, &zero_sf }, /* memory */
{ &sc_rd, &sc_wr, &zero_fo, &zero_sf }, /* sc */
{ &swr_rd, &no_wr, &no_fo, &no_sf }, /* swr */
@@ -255,8 +273,8 @@ struct gdev dev_tab[64] = {
{ &msr_rd, &msr_wr, &zero_fo, &zero_sf }, /* msr */
{ &no_rd, &no_wr, &no_fo, &no_sf }, /* 20 */
{ &no_rd, &no_wr, &no_fo, &no_sf },
{ &no_rd, &no_wr, &no_fo, &no_sf },
{ &no_rd, &no_wr, &no_fo, &no_sf },
{ &xr_rd, &xr_wr, &no_fo, &no_sf }, /* xr */
{ &atrp_rd, &atrp_wr, &no_fo, &no_sf },
{ &bsw_rd, &bsw_wr, &no_fo, &no_sf }, /* bsw */
{ &bpk_rd, &bpk_wr, &no_fo, &no_sf }, /* bpk */
{ &no_rd, &no_wr, &no_fo, &no_sf },
@@ -318,7 +336,7 @@ static const int32 vec_map[16] = {
cpu_mod CPU modifiers list
*/
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX + UNIT_BINK, MAXMEMSIZE) };
UNIT cpu_unit = { UDATA (NULL, UNIT_FIX+UNIT_BINK+UNIT_AO+UNIT_EAO+UNIT_GPR, MAXMEMSIZE) };
REG cpu_reg[] = {
{ ORDATA (SC, SC, 15) },
@@ -336,9 +354,11 @@ REG cpu_reg[] = {
{ ORDATA (GR4, GR[3], 16) },
{ ORDATA (GR5, GR[4], 16) },
{ ORDATA (GR6, GR[5], 16) },
{ ORDATA (XR, XR, 16) },
{ FLDATA (BOV, MSR, MSR_V_BOV) },
{ FLDATA (L, MSR, MSR_V_L) },
{ GRDATA (FOA, MSR, 8, 2, MSR_V_FOA) },
{ FLDATA (SOV, MSR, MSR_V_SOV) },
{ FLDATA (AOV, MSR, MSR_V_AOV) },
{ ORDATA (IR, IR, 16), REG_RO },
{ ORDATA (MA, MA, 16), REG_RO },
@@ -357,8 +377,16 @@ REG cpu_reg[] = {
};
MTAB cpu_mod[] = {
{ UNIT_NOEAO, UNIT_NOEAO, "no EAO", "NOEAO", NULL },
{ UNIT_NOEAO, 0, "EAO", "EAO", NULL },
{ UNIT_GRI99, UNIT_GRI99, "GRI99", "GRI99", NULL },
{ UNIT_GRI99, 0, "GRI909", "GRI909", NULL },
{ UNIT_AO, UNIT_AO, "AO", "AO", NULL },
{ UNIT_AO, 0, "no AO", "NOAO", NULL },
{ UNIT_EAO, UNIT_EAO, "EAO", "EAO", NULL },
{ UNIT_EAO, 0, "no EAO", "NOEAO", NULL },
{ UNIT_GPR, UNIT_GPR, "GPR", "GPR", NULL },
{ UNIT_GPR, 0, "no GPR", "NOGPR", NULL },
{ UNIT_BSWPK, UNIT_BSWPK, "BSW-BPK", "BSW-BPK", NULL },
{ UNIT_BSWPK, 0, "no BSW-BPK", "NOBSW-BPK", NULL },
{ UNIT_MSIZE, 4096, NULL, "4K", &cpu_set_size },
{ UNIT_MSIZE, 8192, NULL, "8K", &cpu_set_size },
{ UNIT_MSIZE, 12288, NULL, "12K", &cpu_set_size },
@@ -488,10 +516,11 @@ while (reason == 0) { /* loop until halted */
SCQ_ENTRY; /* save SC */
SC = (SC + 1) & AMASK; /* incr SC once */
MA = M[SC]; /* get jump addr */
MA = IDX_ADD (MA); /* index? */
if (op & TRP_DEF) { /* defer? */
t = (M[MA] + 1) & DMASK; /* autoinc */
if (MEM_ADDR_OK (MA)) M[MA] = t;
MA = t & AMASK; /* ind addr */
MA = IDX_ADD (t); /* index? */
}
TRP = SC; /* save SC */
SC = MA; /* load new SC */
@@ -515,17 +544,19 @@ while (reason == 0) { /* loop until halted */
switch (op & MEM_MOD) { /* case on addr mode */
case MEM_DIR: /* direct */
MA = M[SC] & AMASK; /* get address */
MA = M[SC]; /* get address */
MA = IDX_ADD (MA); /* index? */
SC = (SC + 1) & AMASK; /* incr SC again */
reason = bus_op (src, op & BUS_FNC, dst); /* xmt and modify */
break;
case MEM_DEF: /* defer */
MA = M[SC] & AMASK; /* get ind addr */
MA = M[SC]; /* get ind addr */
MA = IDX_ADD (MA); /* index? */
SC = (SC + 1) & AMASK; /* incr SC again */
t = (M[MA] + 1) & DMASK; /* autoinc */
if (MEM_ADDR_OK (MA)) M[MA] = t;
MA = t & AMASK; /* ind addr */
MA = IDX_ADD (t); /* index? */
reason = bus_op (src, op & BUS_FNC, dst); /* xmt and modify */
break;
@@ -539,7 +570,7 @@ while (reason == 0) { /* loop until halted */
MA = SC; /* get ind addr */
t = (M[MA] + 1) & DMASK; /* autoinc */
if (MEM_ADDR_OK (MA)) M[MA] = t;
MA = t & AMASK; /* ind addr */
MA = IDX_ADD (t); /* index? */
SC = (SC + 1) & AMASK; /* incr SC again */
reason = bus_op (src, op & BUS_FNC, dst); /* xmt and modify */
break;
@@ -671,6 +702,12 @@ uint32 trp_rd (uint32 src)
return TRP;
}
t_stat trp_wr (uint32 dst, uint32 val)
{
TRP = val;
return SCPE_OK;
}
/* Interrupt status register (04) */
uint32 isr_rd (uint32 src)
@@ -727,7 +764,7 @@ return SC;
t_stat sc_wr (uint32 dst, uint32 dat)
{
SCQ_ENTRY;
SC = dat & AMASK;
SC = IDX_ADD (dat);
return SCPE_OK;
}
@@ -748,11 +785,11 @@ return MSR & MSR_RW;
t_stat msr_wr (uint32 src, uint32 dat)
{
MSR = dat & MSR_RW; /* new MSR */
ao_update (); /* update AOV */
ao_update (); /* update SOV,AOV */
return SCPE_OK;
}
/* Arithmetic operators (11:14) */
/* Arithmetic operator (11:13) */
uint32 ao_update (void)
{
@@ -787,47 +824,70 @@ return AO;
uint32 ax_rd (uint32 src)
{
return AX;
if (cpu_unit.flags & UNIT_AO) return AX;
else return 0;
}
t_stat ax_wr (uint32 dst, uint32 dat)
{
AX = dat;
ao_update ();
return SCPE_OK;
if (cpu_unit.flags & UNIT_AO) {
AX = dat;
ao_update ();
return SCPE_OK;
}
return stop_opr;
}
uint32 ay_rd (uint32 src)
{
return AY;
if (cpu_unit.flags & UNIT_AO) return AY;
else return 0;
}
t_stat ay_wr (uint32 dst, uint32 dat)
{
AY = dat;
ao_update ();
return SCPE_OK;
if (cpu_unit.flags & UNIT_AO) {
AY = dat;
ao_update ();
return SCPE_OK;
}
return stop_opr;
}
uint32 ao_rd (uint32 src)
{
return ao_update ();
if (cpu_unit.flags & UNIT_AO) return ao_update ();
else return 0;
}
t_stat ao_fo (uint32 op)
{
uint32 t = OP_GET_FOA (op); /* get func */
MSR = MSR_PUT_FOA (MSR, t); /* store in MSR */
ao_update (); /* update AOV */
return SCPE_OK;
if (cpu_unit.flags & UNIT_AO) {
uint32 t = OP_GET_FOA (op); /* get func */
MSR = MSR_PUT_FOA (MSR, t); /* store in MSR */
ao_update (); /* update AOV */
return SCPE_OK;
}
return stop_opr;
}
uint32 ao_sf (uint32 op)
{
if (!(cpu_unit.flags & UNIT_AO)) /* not installed? */
return (stop_opr << SF_V_REASON);
if (((op & 2) && (MSR & MSR_AOV)) || /* arith carry? */
((op & 4) && (MSR & MSR_SOV))) return 1; /* arith overflow? */
return 0;
}
/* Extended arithmetic operator (14) */
t_stat eao_fo (uint32 op)
{
uint32 t;
if (cpu_unit.flags & UNIT_NOEAO) return stop_opr; /* EAO installed? */
if (!(cpu_unit.flags & UNIT_EAO)) /* EAO installed? */
return stop_opr;
switch (op) {
case EAO_MUL: /* mul? */
@@ -869,54 +929,94 @@ switch (op) {
break;
}
// MSR = MSR_PUT_FOA (MSR, AO_ADD); /* AO fnc is add */
ao_update ();
return SCPE_OK;
}
uint32 ao_sf (uint32 op)
/* Index register (GRI-99) (22) */
uint32 xr_rd (uint32 src)
{
if (((op & 2) && (MSR & MSR_AOV)) || /* arith carry? */
((op & 4) && (MSR & MSR_SOV))) return 1; /* arith overflow? */
return 0;
if (cpu_unit.flags & UNIT_GRI99) return XR;
else return 0;
}
t_stat xr_wr (uint32 dst, uint32 val)
{
if (cpu_unit.flags & UNIT_GRI99) {
XR = val;
return SCPE_OK;
}
return stop_opr;
}
/* Alternate trap (GRI-99) (23) */
uint32 atrp_rd (uint32 src)
{
if (cpu_unit.flags & UNIT_GRI99) return TRP;
else return 0;
}
t_stat atrp_wr (uint32 dst, uint32 val)
{
if (cpu_unit.flags & UNIT_GRI99) {
TRP = val;
return SCPE_OK;
}
return stop_opr;
}
/* Byte swapper (24) */
uint32 bsw_rd (uint32 src)
{
return BSW;
if (cpu_unit.flags & UNIT_BSWPK) return BSW;
else return 0;
}
t_stat bsw_wr (uint32 dst, uint32 val)
{
BSW = ((val >> 8) & 0377) | ((val & 0377) << 8);
return SCPE_OK;
if (cpu_unit.flags & UNIT_BSWPK) {
BSW = ((val >> 8) & 0377) | ((val & 0377) << 8);
return SCPE_OK;
}
return stop_opr;
}
/* Byte packer (25) */
uint32 bpk_rd (uint32 src)
{
return BPK;
if (cpu_unit.flags & UNIT_BSWPK) return BPK;
else return 0;
}
t_stat bpk_wr (uint32 dst, uint32 val)
{
BPK = ((BPK & 0377) << 8) | (val & 0377);
return SCPE_OK;
if (cpu_unit.flags & UNIT_BSWPK) {
BPK = ((BPK & 0377) << 8) | (val & 0377);
return SCPE_OK;
}
return stop_opr;
}
/* General registers (30:35) */
uint32 gr_rd (uint32 src)
{
return GR[src - U_GR];
if (cpu_unit.flags & UNIT_GPR) return GR[src - U_GR];
else return 0;
}
t_stat gr_wr (uint32 dst, uint32 dat)
{
GR[dst - U_GR] = dat;
return SCPE_OK;
if (cpu_unit.flags & UNIT_GPR) {
GR[dst - U_GR] = dat;
return SCPE_OK;
}
return stop_opr;
}
/* Reset routine */
@@ -926,6 +1026,7 @@ t_stat cpu_reset (DEVICE *dptr)
int32 i;
AX = AY = AO = 0;
XR = 0;
TRP = 0;
ISR = 0;
MSR = 0;

45
GRI/gri_defs.h
View File

@@ -1,6 +1,6 @@
/* gri_defs.h: GRI-909 simulator definitions
Copyright (c) 2001-2004, Robert M. Supnik
Copyright (c) 2001-2008, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
12-Jan-08 RMS Added GRI-99 support
25-Apr-03 RMS Revised for extended file support
19-Sep-02 RMS Fixed declarations in gdev structure
@@ -37,17 +38,12 @@
(SOV). Answer: signed and unsigned.
3. Ref Manual documents a ROM-subroutine multiply operator and mentions
but does not document a "fast multiply"; MITCS uses an extended
arithmetic operator with multiply, divide, and shift. The behavior
of the extended arithmetic operator can only be inferred partially;
the shift is never used, and there is no indication of how divide
overflow is handled. Answer: EAO is a package of ROM subroutines
with just four functions: multiply, divide, arithmetic right shift,
and normalize.
arithmetic operator with multiply, divide, and shift. Answer: EAO
is a package of ROM subroutines with just four functions: multiply,
divide, arithmetic right shift, and normalize.
4. Is SOV testable even if the FOA is not ADD? Answer: AOV and SOV are
calculated regardless of the function.
5. How does the EAO handle divide overflow? Answer: set link.
6. What are the other EAO functions beside multiply and divide?
Answer: arithmetic right shift, normalize.
*/
#include "sim_defs.h" /* simulator defns */
@@ -69,6 +65,7 @@
/* Architectural constants */
#define SIGN 0100000 /* sign */
#define INDEX 0100000 /* indexed (GRI-99) */
#define DMASK 0177777 /* data mask */
#define CBIT (DMASK + 1) /* carry bit */
@@ -105,9 +102,20 @@
#define U_AO 013 /* arith out */
#define U_EAO 014 /* ext arith */
#define U_MSR 017 /* machine status */
#define U_XR 022 /* GRI-99: idx reg */
#define U_GTRP 023 /* GRI-99: alt trap */
#define U_BSW 024 /* byte swap */
#define U_BPK 025 /* byte pack */
#define U_BCP1 026 /* byte compare 1 */
#define U_BCP2 027 /* byte compare 2 */
#define U_GR 030 /* hex general regs */
#define U_CDR 055 /* card reader */
#define U_CADR 057
#define U_DWC 066 /* disk */
#define U_DCA 067
#define U_DISK 070
#define U_LPR 071 /* line printer */
#define U_CAS 074 /* casette */
#define U_RTC 075 /* clock */
#define U_HS 076 /* paper tape */
#define U_TTY 077 /* console */
@@ -173,8 +181,8 @@ struct gdev {
#define MSR_SOV (1u << MSR_V_SOV)
#define MSR_AOV (1u << MSR_V_AOV)
#define MSR_GET_FOA(x) (((x) >> MSR_V_FOA) & MSR_M_FOA)
#define MSR_PUT_FOA(x,n) (((x) & ~(MSR_M_FOA << MSR_V_FOA)) | \
(((n) & MSR_M_FOA) << MSR_V_FOA))
#define MSR_PUT_FOA(x,n) (((x) & ~(MSR_M_FOA << MSR_V_FOA)) | \
(((n) & MSR_M_FOA) << MSR_V_FOA))
#define MSR_RW (MSR_BOV|MSR_L|MSR_FOA|MSR_SOV|MSR_AOV)
/* Real time clock */
@@ -201,14 +209,24 @@ struct gdev {
#define INT_V_TTI 1 /* console in */
#define INT_V_HSP 2 /* paper tape punch */
#define INT_V_HSR 3 /* paper tape reader */
#define INT_V_LPR 5 /* line printer */
#define INT_V_CDR 7 /* card reader */
#define INT_V_CASW 9 /* casette */
#define INT_V_CASR 10
#define INT_V_RTC 11 /* clock */
#define INT_V_DISK 14 /* disk */
#define INT_V_NODEF 16 /* nodefer */
#define INT_V_ON 17 /* enable */
#define INT_TTO (1u << INT_V_TTO)
#define INT_TTI (1u << INT_V_TTI)
#define INT_HSP (1u << INT_V_HSP)
#define INT_HSR (1u << INT_V_HSR)
#define INT_LPR (1u << INT_V_LPR)
#define INT_CDR (1u << INT_V_CDR)
#define INT_CASW (1u << INT_V_CAS1)
#define INT_CASR (1u << INT_V_CAS2)
#define INT_RTC (1u << INT_V_RTC)
#define INT_DISK (1u << INT_V_DISK)
#define INT_NODEF (1u << INT_V_NODEF)
#define INT_ON (1u << INT_V_ON)
#define INT_PENDING (INT_ON | INT_NODEF)
@@ -220,4 +238,9 @@ struct gdev {
#define VEC_TTI 0014 /* console in */
#define VEC_HSP 0017 /* paper tape punch */
#define VEC_HSR 0022 /* paper tape reader */
#define VEC_LPR 0033 /* line printer */
#define VEC_CDR 0033 /* card reader */
#define VEC_CASW 0044 /* casette */
#define VEC_CASR 0047
#define VEC_DISK 0055 /* disk */
#define VEC_RTC 0100 /* clock */

9
GRI/gri_stddev.c
View File

@@ -1,6 +1,6 @@
/* gri_stddev.c: GRI-909 standard devices
Copyright (c) 2001-2006, Robert M Supnik
Copyright (c) 2001-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -29,6 +29,7 @@
hsp S42-006 high speed punch
rtc real time clock
31-May-08 RMS Fixed declarations (found by Peter Schorn)
30-Sep-06 RMS Fixed handling of non-printable characters in KSR mode
22-Nov-05 RMS Revised for new terminal processing routines
29-Dec-03 RMS Added support for console backpressure
@@ -208,7 +209,7 @@ DEVICE rtc_dev = {
/* Console terminal function processors */
int32 tty_rd (int32 src, int32 ea)
uint32 tty_rd (int32 src, int32 ea)
{
return tti_unit.buf; /* return data */
}
@@ -294,7 +295,7 @@ return SCPE_OK;
/* High speed paper tape function processors */
int32 hsrp_rd (int32 src, int32 ea)
uint32 hsrp_rd (int32 src, int32 ea)
{
return hsr_unit.buf; /* return data */
}
@@ -386,7 +387,7 @@ if (op & RTC_OV) dev_done = dev_done & ~INT_RTC; /* clr ovflo? */
return SCPE_OK;
}
int32 rtc_sf (int32 op)
uint32 rtc_sf (int32 op)
{
if ((op & RTC_OV) && (dev_done & INT_RTC)) return 1;
return 0;

72
GRI/gri_sys.c
View File

@@ -1,6 +1,6 @@
/* gri_sys.c: GRI-909 simulator interface
Copyright (c) 2001-2005, Robert M Supnik
Copyright (c) 2001-2008, Robert M Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@@ -23,6 +23,7 @@
used in advertising or otherwise to promote the sale, use or other dealings
in this Software without prior written authorization from Robert M Supnik.
14-Jan-08 RMS Added GRI-99 support
18-Oct-02 RMS Fixed bug in symbolic decode (found by Hans Pufal)
*/
@@ -38,6 +39,8 @@ extern REG cpu_reg[];
extern uint16 M[];
extern int32 sim_switches;
void fprint_addr (FILE *of, uint32 val, uint32 mod, uint32 dst);
/* SCP data structures and interface routines
sim_name simulator name string
@@ -210,26 +213,26 @@ static const uint32 opc_val[] = {
static const char *unsrc[64] = {
"0", "IR", "2", "TRP", "ISR", "MA", "MB", "SC", /* 00 - 07 */
"SWR", "AX", "AY", "AO", "14", "15", "16", "MSR", /* 10 - 17 */
"20", "21", "22", "23", "BSW", "BPK", "26", "27", /* 20 - 27 */
"20", "21", "XR", "ATRP", "BSW", "BPK", "BCPA", "BCPB",/* 20 - 27 */
"GR1", "GR2", "GR3", "GR4", "GR5", "GR6", "36", "37", /* 30 - 37 */
"40", "41", "42", "43", "44", "45", "46", "47",
"50", "51", "52", "53", "54", "55", "56", "57",
"60", "61", "62", "63", "64", "65", "66", "67",
"70", "71", "72", "73", "74", "RTC", "HSR", "TTI" /* 70 - 77 */
"50", "51", "52", "53", "54", "CDR", "56", "CADR",
"60", "61", "62", "63", "64", "65", "DWC", "DCA",
"DISK", "LPR", "72", "73", "CAS", "RTC", "HSR", "TTI" /* 70 - 77 */
};
static const char *undst[64] = {
"0", "IR", "2", "TRP", "ISR", "5", "MB", "SC", /* 00 - 07 */
"SWR", "AX", "AY", "13", "EAO", "15", "16", "MSR", /* 10 - 17 */
"20", "21", "22", "23", "BSW", "BPK", "26", "27", /* 20 - 27 */
"20", "21", "XR", "ATRP", "BSW", "BPK", "BCPA", "BCPB",/* 20 - 27 */
"GR1", "GR2", "GR3", "GR4", "GR5", "GR6", "36", "37", /* 30 - 37 */
"40", "41", "42", "43", "44", "45", "46", "47",
"50", "51", "52", "53", "54", "55", "56", "57",
"60", "61", "62", "63", "64", "65", "66", "67",
"70", "71", "72", "73", "74", "RTC", "HSP", "TTO" /* 70 - 77 */
"50", "51", "52", "53", "54", "CDR", "56", "CADR",
"60", "61", "62", "63", "64", "65", "DWC", "DCA",
"DISK", "LPR", "72", "73", "CAS", "RTC", "HSP", "TTO" /* 70 - 77 */
};
/* Operators */
/* Operators */
static const char *opname[4] = {
NULL, "P1", "L1", "R1"
@@ -299,6 +302,17 @@ if (op) fprintf (of, " %o", op);
return;
}
/* Print address field with potential indexing */
void fprint_addr (FILE *of, uint32 val, uint32 mode, uint32 dst)
{
if ((val & INDEX) &&
((dst == U_SC) || (mode != MEM_IMM)))
fprintf (of, "#%o", val & AMASK);
else fprintf (of, "%o", val);
return;
}
/* Symbolic decode
Inputs:
@@ -387,36 +401,40 @@ for (i = 0; opcode[i] != NULL; i++) { /* loop thru ops */
break;
case F_V_JC: /* jump cond */
fprintf (of, "%s %s,%s,%o", opcode[i],
unsrc[src], cdname[op >> 1], val[1]);
fprintf (of, "%s %s,%s,",
opcode[i], unsrc[src], cdname[op >> 1]);
fprint_addr (of, val[1], 0, U_SC);
break;
case F_V_JU: /* jump uncond */
fprintf (of, "%s %o", opcode[i], val[1]);
fprintf (of, "%s ", opcode[i]);
fprint_addr (of, val[1], 0, U_SC);
break;
case F_V_RM: /* reg mem */
if (bop) fprintf (of, "%s %s,%s,%o", opcode[i],
unsrc[src], opname[bop], val[1]);
else fprintf (of, "%s %s,%o", opcode[i], unsrc[src], val[1]);
if (bop) fprintf (of, "%s %s,%s,",
opcode[i], unsrc[src], opname[bop]);
else fprintf (of, "%s %s,", opcode[i], unsrc[src]);
fprint_addr (of, val[1], op & MEM_MOD, dst);
break;
case F_V_ZM: /* zero mem */
if (bop) fprintf (of, "%s %s,%o", opcode[i],
opname[bop], val[1]);
else fprintf (of, "%s %o", opcode[i], val[1]);
if (bop) fprintf (of, "%s %s,", opcode[i], opname[bop]);
else fprintf (of, "%s ", opcode[i]);
fprint_addr (of, val[1], op & MEM_MOD, dst);
break;
case F_V_MR: /* mem reg */
if (bop) fprintf (of, "%s %o,%s,%s", opcode[i],
val[1], opname[bop], undst[dst]);
else fprintf (of, "%s %o,%s", opcode[i], val[1], undst[dst]);
fprintf (of, "%s ", opcode[i]);
fprint_addr (of, val[1], op & MEM_MOD, dst);
if (bop) fprintf (of, ",%s,%s", opname[bop], undst[dst]);
else fprintf (of, ",%s", undst[dst]);
break;
case F_V_MS: /* mem self */
if (bop) fprintf (of, "%s %o,%s", opcode[i],
val[1], opname[bop]);
else fprintf (of, "%s %o", opcode[i], val[1]);
fprintf (of, "%s ", opcode[i]);
fprint_addr (of, val[1], op & MEM_MOD, dst);
if (bop) fprintf (of, ",%s", opname[bop]);
break;
} /* end case */
@@ -475,7 +493,9 @@ t_value d;
t_stat r;
cptr = get_glyph (cptr, gbuf, term); /* get glyph */
d = get_uint (gbuf, 8, DMASK, &r); /* [0,177777] */
if (gbuf[0] == '#') /* indexed? */
d = get_uint (gbuf + 1, 8, AMASK, &r) | INDEX; /* [0, 77777] */
else d = get_uint (gbuf, 8, DMASK, &r); /* [0,177777] */
if (r != SCPE_OK) return NULL;
val[1] = d; /* second wd */
return cptr;