mirror of
https://github.com/open-simh/simh.git
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Notes For V3.8
The makefile now works for Linux and most Unix's. Howevr, for Solaris and MacOS, you must first export the OSTYPE environment variable: > export OSTYPE > make Otherwise, you will get build errors. 1. New Features 1.1 3.8-0 1.1.1 SCP and Libraries - BREAK, NOBREAK, and SHOW BREAK with no argument will set, clear, and show (respectively) a breakpoint at the current PC. 1.2 GRI - Added support for the GRI-99 processor. 1.3 HP2100 - Added support for the BACI terminal interface. - Added support for RTE OS/VMA/EMA, SIGNAL, VIS firmware extensions. 1.4 Nova - Added support for 64KW memory (implemented in third-party CPU's). 1.5 PDP-11 - Added support for DC11, RC11, KE11A, KG11A. - Added modem control support for DL11. - Added ASCII character support for all 8b devices. 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
3cb7c60d5d
commit
59aa4a73b1
543
PDP11/pdp11_dl.c
543
PDP11/pdp11_dl.c
@@ -23,9 +23,10 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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ttix,ttox DL11 terminal input/output
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*/
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dli,dlo DL11 terminal input/output
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20-May-2008 RMS Added modem control support
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*/
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#if defined (VM_PDP10) /* PDP10 version */
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#error "DL11 is not supported on the PDP-10!"
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@@ -39,198 +40,258 @@
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#include "sim_sock.h"
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#include "sim_tmxr.h"
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#define TTX_MASK (TTX_LINES - 1)
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#define DLX_MASK (DLX_LINES - 1)
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#define DLI_RCI 0 /* rcv ints */
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#define DLI_DSI 1 /* dset ints */
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#define TTIXCSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTIXCSR_RW (CSR_IE)
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#define TTIXBUF_ERR 0100000
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#define TTIXBUF_OVR 0040000
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#define TTIXBUF_RBRK 0020000
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#define TTOXCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOXCSR_RW (CSR_IE)
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/* Modem control */
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#define DLX_V_MDM (TTUF_V_UF + 0)
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#define DLX_MDM (1u << DLX_V_MDM)
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/* registers */
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#define DLICSR_DSI 0100000 /* dataset int, RO */
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#define DLICSR_RNG 0040000 /* ring, RO */
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#define DLICSR_CTS 0020000 /* CTS, RO */
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#define DLICSR_CDT 0010000 /* CDT, RO */
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#define DLICSR_SEC 0002000 /* sec rcv, RONI */
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#define DLICSR_DSIE 0000040 /* DSI ie, RW */
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#define DLICSR_SECX 0000010 /* sec xmt, RWNI */
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#define DLICSR_RTS 0000004 /* RTS, RW */
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#define DLICSR_DTR 0000002 /* DTR, RW */
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#define DLICSR_RD (CSR_DONE|CSR_IE) /* DL11C */
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#define DLICSR_WR (CSR_IE)
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#define DLICSR_RD_M (DLICSR_DSI|DLICSR_RNG|DLICSR_CTS|DLICSR_CDT|DLICSR_SEC| \
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CSR_DONE|CSR_IE|DLICSR_DSIE|DLICSR_SECX|DLICSR_RTS|DLICSR_DTR)
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#define DLICSR_WR_M (CSR_IE|DLICSR_DSIE|DLICSR_SECX|DLICSR_RTS|DLICSR_DTR)
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#define DLIBUF_ERR 0100000
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#define DLIBUF_OVR 0040000
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#define DLIBUF_RBRK 0020000
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#define DLIBUF_RD (DLIBUF_ERR|DLIBUF_OVR|DLIBUF_RBRK|0377)
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#define DLOCSR_MNT 0000004 /* maint, RWNI */
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#define DLOCSR_XBR 0000001 /* xmit brk, RWNI */
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#define DLOCSR_RD (CSR_DONE|CSR_IE|DLOCSR_MNT|DLOCSR_XBR)
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#define DLOCSR_WR (CSR_IE|DLOCSR_MNT|DLOCSR_XBR)
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extern int32 int_req[IPL_HLVL];
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extern int32 tmxr_poll;
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uint16 ttix_csr[TTX_LINES] = { 0 }; /* control/status */
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uint16 ttix_buf[TTX_LINES] = { 0 };
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uint32 ttix_ireq = 0;
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uint16 ttox_csr[TTX_LINES] = { 0 }; /* control/status */
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uint8 ttox_buf[TTX_LINES] = { 0 };
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uint32 ttox_ireq = 0;
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TMLN ttx_ldsc[TTX_LINES] = { 0 }; /* line descriptors */
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TMXR ttx_desc = { TTX_LINES, 0, 0, ttx_ldsc }; /* mux descriptor */
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uint16 dli_csr[DLX_LINES] = { 0 }; /* control/status */
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uint16 dli_buf[DLX_LINES] = { 0 };
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uint32 dli_ireq[2] = { 0, 0};
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uint16 dlo_csr[DLX_LINES] = { 0 }; /* control/status */
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uint8 dlo_buf[DLX_LINES] = { 0 };
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uint32 dlo_ireq = 0;
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TMLN dlx_ldsc[DLX_LINES] = { 0 }; /* line descriptors */
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TMXR dlx_desc = { DLX_LINES, 0, 0, dlx_ldsc }; /* mux descriptor */
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t_stat ttx_rd (int32 *data, int32 PA, int32 access);
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t_stat ttx_wr (int32 data, int32 PA, int32 access);
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t_stat ttx_reset (DEVICE *dptr);
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t_stat ttix_svc (UNIT *uptr);
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t_stat ttox_svc (UNIT *uptr);
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t_stat ttx_attach (UNIT *uptr, char *cptr);
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t_stat ttx_detach (UNIT *uptr);
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t_stat ttx_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat ttx_show (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat ttx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat ttx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat ttx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc);
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void ttx_enbdis (int32 dis);
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void ttix_clr_int (uint32 ln);
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void ttix_set_int (int32 ln);
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int32 ttix_iack (void);
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void ttox_clr_int (int32 ln);
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void ttox_set_int (int32 ln);
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int32 ttox_iack (void);
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void ttx_reset_ln (uint32 ln);
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t_stat dlx_rd (int32 *data, int32 PA, int32 access);
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t_stat dlx_wr (int32 data, int32 PA, int32 access);
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t_stat dlx_reset (DEVICE *dptr);
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t_stat dli_svc (UNIT *uptr);
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t_stat dlo_svc (UNIT *uptr);
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t_stat dlx_attach (UNIT *uptr, char *cptr);
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t_stat dlx_detach (UNIT *uptr);
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t_stat dlx_summ (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dlx_show (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dlx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);
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t_stat dlx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat dlx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc);
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void dlx_enbdis (int32 dis);
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void dli_clr_int (int32 ln, uint32 wd);
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void dli_set_int (int32 ln, uint32 wd);
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int32 dli_iack (void);
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void dlo_clr_int (int32 ln);
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void dlo_set_int (int32 ln);
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int32 dlo_iack (void);
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void dlx_reset_ln (int32 ln);
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/* TTIX data structures
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/* DLI data structures
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ttix_dev TTIX device descriptor
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ttix_unit TTIX unit descriptor
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ttix_reg TTIX register list
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dli_dev DLI device descriptor
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dli_unit DLI unit descriptor
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dli_reg DLI register list
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*/
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DIB ttix_dib = {
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IOBA_TTIX, IOLN_TTIX, &ttx_rd, &ttx_wr,
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2, IVCL (TTIX), VEC_TTIX, { &ttix_iack, &ttox_iack }
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DIB dli_dib = {
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IOBA_DL, IOLN_DL, &dlx_rd, &dlx_wr,
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2, IVCL (DLI), VEC_DLI, { &dli_iack, &dlo_iack }
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};
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UNIT ttix_unit = { UDATA (&ttix_svc, 0, 0), KBD_POLL_WAIT };
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UNIT dli_unit = { UDATA (&dli_svc, 0, 0), KBD_POLL_WAIT };
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REG ttix_reg[] = {
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{ BRDATA (BUF, ttix_buf, DEV_RDX, 16, TTX_LINES) },
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{ BRDATA (CSR, ttix_csr, DEV_RDX, 16, TTX_LINES) },
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{ GRDATA (IREQ, ttix_ireq, DEV_RDX, TTX_LINES, 0) },
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{ DRDATA (LINES, ttx_desc.lines, 6), REG_HRO },
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{ GRDATA (DEVADDR, ttix_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVVEC, ttix_dib.vec, DEV_RDX, 16, 0), REG_HRO },
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REG dli_reg[] = {
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{ BRDATA (BUF, dli_buf, DEV_RDX, 16, DLX_LINES) },
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{ BRDATA (CSR, dli_csr, DEV_RDX, 16, DLX_LINES) },
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{ GRDATA (IREQ, dli_ireq[DLI_RCI], DEV_RDX, DLX_LINES, 0) },
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{ GRDATA (DSI, dli_ireq[DLI_DSI], DEV_RDX, DLX_LINES, 0) },
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{ DRDATA (LINES, dlx_desc.lines, 6), REG_HRO },
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{ GRDATA (DEVADDR, dli_dib.ba, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVIOLN, dli_dib.lnt, DEV_RDX, 32, 0), REG_HRO },
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{ GRDATA (DEVVEC, dli_dib.vec, DEV_RDX, 16, 0), REG_HRO },
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{ NULL }
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};
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MTAB ttix_mod[] = {
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{ UNIT_ATT, UNIT_ATT, "summary", NULL, NULL, &ttx_summ },
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MTAB dli_mod[] = {
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{ UNIT_ATT, UNIT_ATT, "summary", NULL, NULL, &dlx_summ },
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{ MTAB_XTD | MTAB_VDV, 1, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &ttx_desc },
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&tmxr_dscln, NULL, &dlx_desc },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 1, "CONNECTIONS", NULL,
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NULL, &ttx_show, NULL },
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NULL, &dlx_show, NULL },
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{ MTAB_XTD | MTAB_VDV | MTAB_NMO, 0, "STATISTICS", NULL,
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NULL, &ttx_show, NULL },
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NULL, &dlx_show, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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&set_addr, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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&set_vec, &ttx_show_vec, NULL },
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&set_vec, &dlx_show_vec, NULL },
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{ MTAB_XTD | MTAB_VDV, 0, "lines", "LINES",
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&ttx_set_lines, &ttx_show_lines },
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&dlx_set_lines, &dlx_show_lines },
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{ 0 }
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};
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DEVICE ttix_dev = {
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"TTIX", &ttix_unit, ttix_reg, ttix_mod,
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DEVICE dli_dev = {
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"DLI", &dli_unit, dli_reg, dli_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &ttx_reset,
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NULL, &ttx_attach, &ttx_detach,
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&ttix_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
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NULL, NULL, &dlx_reset,
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NULL, &dlx_attach, &dlx_detach,
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&dli_dib, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
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};
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/* TTOX data structures
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/* DLO data structures
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ttox_dev TTOX device descriptor
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ttox_unit TTOX unit descriptor
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ttox_reg TTOX register list
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dlo_dev DLO device descriptor
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dlo_unit DLO unit descriptor
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dlo_reg DLO register list
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*/
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UNIT ttox_unit[] = {
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&ttox_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT }
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UNIT dlo_unit[] = {
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT },
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{ UDATA (&dlo_svc, TT_MODE_UC, 0), SERIAL_OUT_WAIT }
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};
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REG ttox_reg[] = {
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{ BRDATA (BUF, ttox_buf, DEV_RDX, 8, TTX_LINES) },
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{ BRDATA (CSR, ttox_csr, DEV_RDX, 16, TTX_LINES) },
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{ GRDATA (IREQ, ttox_ireq, DEV_RDX, TTX_LINES, 0) },
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{ URDATA (TIME, ttox_unit[0].wait, 10, 31, 0,
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TTX_LINES, PV_LEFT) },
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REG dlo_reg[] = {
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{ BRDATA (BUF, dlo_buf, DEV_RDX, 8, DLX_LINES) },
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{ BRDATA (CSR, dlo_csr, DEV_RDX, 16, DLX_LINES) },
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{ GRDATA (IREQ, dlo_ireq, DEV_RDX, DLX_LINES, 0) },
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{ URDATA (TIME, dlo_unit[0].wait, 10, 31, 0,
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DLX_LINES, PV_LEFT) },
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{ NULL }
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};
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MTAB ttox_mod[] = {
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MTAB dlo_mod[] = {
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{ TT_MODE, TT_MODE_UC, "UC", "UC", NULL },
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{ TT_MODE, TT_MODE_7B, "7b", "7B", NULL },
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{ TT_MODE, TT_MODE_8B, "8b", "8B", NULL },
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{ TT_MODE, TT_MODE_7P, "7p", "7P", NULL },
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{ DLX_MDM, 0, "no dataset", "NODATASET", NULL },
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{ DLX_MDM, DLX_MDM, "dataset", "DATASET", NULL },
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{ MTAB_XTD|MTAB_VUN, 0, NULL, "DISCONNECT",
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&tmxr_dscln, NULL, &ttx_desc },
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&tmxr_dscln, NULL, &dlx_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, "LOG", "LOG",
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&tmxr_set_log, &tmxr_show_log, &ttx_desc },
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&tmxr_set_log, &tmxr_show_log, &dlx_desc },
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{ MTAB_XTD|MTAB_VUN|MTAB_NC, 0, NULL, "NOLOG",
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&tmxr_set_nolog, NULL, &ttx_desc },
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&tmxr_set_nolog, NULL, &dlx_desc },
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{ 0 }
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};
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DEVICE ttox_dev = {
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"TTOX", ttox_unit, ttox_reg, ttox_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &ttx_reset,
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DEVICE dlo_dev = {
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"DLO", dlo_unit, dlo_reg, dlo_mod,
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DLX_LINES, 10, 31, 1, 8, 8,
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NULL, NULL, &dlx_reset,
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NULL, NULL, NULL,
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NULL, DEV_UBUS | DEV_QBUS | DEV_DISABLE | DEV_DIS
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};
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/* Terminal input routines */
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t_stat ttx_rd (int32 *data, int32 PA, int32 access)
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t_stat dlx_rd (int32 *data, int32 PA, int32 access)
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{
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uint32 ln = ((PA - ttix_dib.ba) >> 3) & TTX_MASK;
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int32 ln = ((PA - dli_dib.ba) >> 3) & DLX_MASK;
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switch ((PA >> 1) & 03) { /* decode PA<2:1> */
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case 00: /* tti csr */
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*data = ttix_csr[ln] & TTIXCSR_IMP;
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*data = dli_csr[ln] &
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((dlo_unit[ln].flags & DLX_MDM)? DLICSR_RD_M: DLICSR_RD);
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dli_csr[ln] &= ~DLICSR_DSI; /* clr DSI flag */
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dli_clr_int (ln, DLI_DSI); /* clr dset int req */
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return SCPE_OK;
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case 01: /* tti buf */
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ttix_csr[ln] &= ~CSR_DONE;
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ttix_clr_int (ln);
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*data = ttix_buf[ln];
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*data = dli_buf[ln] & DLIBUF_RD;
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dli_csr[ln] &= ~CSR_DONE; /* clr rcv done */
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dli_clr_int (ln, DLI_RCI); /* clr rcv int req */
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||||
return SCPE_OK;
|
||||
|
||||
case 02: /* tto csr */
|
||||
*data = ttox_csr[ln] & TTOXCSR_IMP;
|
||||
*data = dlo_csr[ln] & DLOCSR_RD;
|
||||
return SCPE_OK;
|
||||
|
||||
case 03: /* tto buf */
|
||||
*data = ttox_buf[ln];
|
||||
*data = dlo_buf[ln];
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
t_stat ttx_wr (int32 data, int32 PA, int32 access)
|
||||
t_stat dlx_wr (int32 data, int32 PA, int32 access)
|
||||
{
|
||||
uint32 ln = ((PA - ttix_dib.ba) >> 3) & TTX_MASK;
|
||||
int32 ln = ((PA - dli_dib.ba) >> 3) & DLX_MASK;
|
||||
TMLN *lp = &dlx_ldsc[ln];
|
||||
|
||||
switch ((PA >> 1) & 03) { /* decode PA<2:1> */
|
||||
|
||||
case 00: /* tti csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if (PA & 1) return SCPE_OK; /* odd byte RO */
|
||||
if ((data & CSR_IE) == 0)
|
||||
ttix_clr_int (ln);
|
||||
else if ((ttix_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
ttix_set_int (ln);
|
||||
ttix_csr[ln] = (uint16) ((ttix_csr[ln] & ~TTIXCSR_RW) | (data & TTIXCSR_RW));
|
||||
dli_clr_int (ln, DLI_RCI);
|
||||
else if ((dli_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
dli_set_int (ln, DLI_RCI);
|
||||
if (dlo_unit[ln].flags & DLX_MDM) { /* modem control */
|
||||
if ((data & DLICSR_DSIE) == 0)
|
||||
dli_clr_int (ln, DLI_DSI);
|
||||
else if ((dli_csr[ln] & (DLICSR_DSI|DLICSR_DSIE)) == DLICSR_DSI)
|
||||
dli_set_int (ln, DLI_DSI);
|
||||
if ((data ^ dli_csr[ln]) & DLICSR_DTR) { /* DTR change? */
|
||||
if ((data & DLICSR_DTR) && lp->conn) { /* setting DTR? */
|
||||
dli_csr[ln] = (dli_csr[ln] & ~DLICSR_RNG) |
|
||||
(DLICSR_CDT|DLICSR_CTS|DLICSR_DSI);
|
||||
if (data & DLICSR_DSIE) /* if ie, req int */
|
||||
dli_set_int (ln, DLI_DSI);
|
||||
} /* end DTR 0->1 + ring */
|
||||
else { /* clearing DTR */
|
||||
if (lp->conn) { /* connected? */
|
||||
tmxr_linemsg (lp, "\r\nLine hangup\r\n");
|
||||
tmxr_reset_ln (lp); /* reset line */
|
||||
if (dli_csr[ln] & DLICSR_CDT) { /* carrier det? */
|
||||
dli_csr[ln] |= DLICSR_DSI;
|
||||
if (data & DLICSR_DSIE) /* if ie, req int */
|
||||
dli_set_int (ln, DLI_DSI);
|
||||
}
|
||||
}
|
||||
dli_csr[ln] &= ~(DLICSR_CDT|DLICSR_RNG|DLICSR_CTS);
|
||||
/* clr CDT,RNG,CTS */
|
||||
} /* end DTR 1->0 */
|
||||
} /* end DTR chg */
|
||||
dli_csr[ln] = (uint16) ((dli_csr[ln] & ~DLICSR_WR_M) | (data & DLICSR_WR_M));
|
||||
} /* end modem */
|
||||
dli_csr[ln] = (uint16) ((dli_csr[ln] & ~DLICSR_WR) | (data & DLICSR_WR));
|
||||
return SCPE_OK;
|
||||
|
||||
case 01: /* tti buf */
|
||||
@@ -239,18 +300,18 @@ switch ((PA >> 1) & 03) { /* decode PA<2:1> */
|
||||
case 02: /* tto csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if ((data & CSR_IE) == 0)
|
||||
ttox_clr_int (ln);
|
||||
else if ((ttox_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
ttox_set_int (ln);
|
||||
ttox_csr[ln] = (uint16) ((ttox_csr[ln] & ~TTOXCSR_RW) | (data & TTOXCSR_RW));
|
||||
dlo_clr_int (ln);
|
||||
else if ((dlo_csr[ln] & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
dlo_set_int (ln);
|
||||
dlo_csr[ln] = (uint16) ((dlo_csr[ln] & ~DLOCSR_WR) | (data & DLOCSR_WR));
|
||||
return SCPE_OK;
|
||||
|
||||
case 03: /* tto buf */
|
||||
if ((PA & 1) == 0)
|
||||
ttox_buf[ln] = data & 0377;
|
||||
ttox_csr[ln] &= ~CSR_DONE;
|
||||
ttox_clr_int (ln);
|
||||
sim_activate (&ttox_unit[ln], ttox_unit[ln].wait);
|
||||
dlo_buf[ln] = data & 0377;
|
||||
dlo_csr[ln] &= ~CSR_DONE;
|
||||
dlo_clr_int (ln);
|
||||
sim_activate (&dlo_unit[ln], dlo_unit[ln].wait);
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
@@ -259,112 +320,132 @@ return SCPE_NXM;
|
||||
|
||||
/* Terminal input service */
|
||||
|
||||
t_stat ttix_svc (UNIT *uptr)
|
||||
t_stat dli_svc (UNIT *uptr)
|
||||
{
|
||||
int32 ln, c, temp;
|
||||
|
||||
if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK; /* attached? */
|
||||
sim_activate (uptr, tmxr_poll); /* continue poll */
|
||||
ln = tmxr_poll_conn (&ttx_desc); /* look for connect */
|
||||
if (ln >= 0) ttx_ldsc[ln].rcve = 1; /* got one? rcv enb */
|
||||
tmxr_poll_rx (&ttx_desc); /* poll for input */
|
||||
for (ln = 0; ln < TTX_LINES; ln++) { /* loop thru lines */
|
||||
if (ttx_ldsc[ln].conn) { /* connected? */
|
||||
if (temp = tmxr_getc_ln (&ttx_ldsc[ln])) { /* get char */
|
||||
ln = tmxr_poll_conn (&dlx_desc); /* look for connect */
|
||||
if (ln >= 0) { /* got one? rcv enb */
|
||||
dlx_ldsc[ln].rcve = 1;
|
||||
if (dlo_unit[ln].flags & DLX_MDM) { /* modem control? */
|
||||
if (dli_csr[ln] & DLICSR_DTR) /* DTR already set? */
|
||||
dli_csr[ln] |= (DLICSR_CDT|DLICSR_CTS|DLICSR_DSI);
|
||||
else dli_csr[ln] |= (DLICSR_RNG|DLICSR_DSI); /* no, ring */
|
||||
if (dli_csr[ln] & DLICSR_DSIE) /* if ie, */
|
||||
dli_set_int (ln, DLI_DSI); /* req int */
|
||||
} /* end modem */
|
||||
} /* end new conn */
|
||||
tmxr_poll_rx (&dlx_desc); /* poll for input */
|
||||
for (ln = 0; ln < DLX_LINES; ln++) { /* loop thru lines */
|
||||
if (dlx_ldsc[ln].conn) { /* connected? */
|
||||
if (temp = tmxr_getc_ln (&dlx_ldsc[ln])) { /* get char */
|
||||
if (temp & SCPE_BREAK) /* break? */
|
||||
c = TTIXBUF_ERR|TTIXBUF_RBRK;
|
||||
else c = sim_tt_inpcvt (temp, TT_GET_MODE (ttox_unit[ln].flags));
|
||||
if (ttix_csr[ln] & CSR_DONE)
|
||||
c |= TTIXBUF_ERR|TTIXBUF_OVR;
|
||||
else {
|
||||
ttix_csr[ln] |= CSR_DONE;
|
||||
if (ttix_csr[ln] & CSR_IE) ttix_set_int (ln);
|
||||
}
|
||||
ttix_buf[ln] = c;
|
||||
c = DLIBUF_ERR|DLIBUF_RBRK;
|
||||
else c = sim_tt_inpcvt (temp, TT_GET_MODE (dlo_unit[ln].flags));
|
||||
if (dli_csr[ln] & CSR_DONE)
|
||||
c |= DLIBUF_ERR|DLIBUF_OVR;
|
||||
else dli_csr[ln] |= CSR_DONE;
|
||||
if (dli_csr[ln] & CSR_IE)
|
||||
dli_set_int (ln, DLI_RCI);
|
||||
dli_buf[ln] = c;
|
||||
}
|
||||
}
|
||||
else if (dlo_unit[ln].flags & DLX_MDM) { /* discpnn & modem? */
|
||||
if (dli_csr[ln] & DLICSR_CDT) { /* carrier detect? */
|
||||
dli_csr[ln] |= DLICSR_DSI; /* dataset change */
|
||||
if (dli_csr[ln] & DLICSR_DSIE) /* if ie, */
|
||||
dli_set_int (ln, DLI_DSI); /* req int */
|
||||
}
|
||||
dli_csr[ln] &= ~(DLICSR_CDT|DLICSR_RNG|DLICSR_CTS);
|
||||
/* clr CDT,RNG,CTS */
|
||||
}
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Terminal output service */
|
||||
|
||||
t_stat ttox_svc (UNIT *uptr)
|
||||
t_stat dlo_svc (UNIT *uptr)
|
||||
{
|
||||
int32 c;
|
||||
uint32 ln = uptr - ttox_unit; /* line # */
|
||||
int32 ln = uptr - dlo_unit; /* line # */
|
||||
|
||||
if (ttx_ldsc[ln].conn) { /* connected? */
|
||||
if (ttx_ldsc[ln].xmte) { /* tx enabled? */
|
||||
TMLN *lp = &ttx_ldsc[ln]; /* get line */
|
||||
c = sim_tt_outcvt (ttox_buf[ln], TT_GET_MODE (ttox_unit[ln].flags));
|
||||
if (dlx_ldsc[ln].conn) { /* connected? */
|
||||
if (dlx_ldsc[ln].xmte) { /* tx enabled? */
|
||||
TMLN *lp = &dlx_ldsc[ln]; /* get line */
|
||||
c = sim_tt_outcvt (dlo_buf[ln], TT_GET_MODE (dlo_unit[ln].flags));
|
||||
if (c >= 0) tmxr_putc_ln (lp, c); /* output char */
|
||||
tmxr_poll_tx (&ttx_desc); /* poll xmt */
|
||||
tmxr_poll_tx (&dlx_desc); /* poll xmt */
|
||||
}
|
||||
else {
|
||||
tmxr_poll_tx (&ttx_desc); /* poll xmt */
|
||||
sim_activate (uptr, ttox_unit[ln].wait); /* wait */
|
||||
tmxr_poll_tx (&dlx_desc); /* poll xmt */
|
||||
sim_activate (uptr, dlo_unit[ln].wait); /* wait */
|
||||
return SCPE_OK;
|
||||
}
|
||||
}
|
||||
ttox_csr[ln] |= CSR_DONE; /* set done */
|
||||
if (ttox_csr[ln] & CSR_IE) ttox_set_int (ln);
|
||||
dlo_csr[ln] |= CSR_DONE; /* set done */
|
||||
if (dlo_csr[ln] & CSR_IE)
|
||||
dlo_set_int (ln);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
/* Interrupt routines */
|
||||
|
||||
void ttix_clr_int (uint32 ln)
|
||||
void dli_clr_int (int32 ln, uint32 wd)
|
||||
{
|
||||
ttix_ireq &= ~(1 << ln); /* clr mux rcv int */
|
||||
if (ttix_ireq == 0) CLR_INT (TTIX); /* all clr? */
|
||||
else SET_INT (TTIX); /* no, set intr */
|
||||
dli_ireq[wd] &= ~(1 << ln); /* clr rcv/dset int */
|
||||
if ((dli_ireq[DLI_RCI] | dli_ireq[DLI_DSI]) == 0) /* all clr? */
|
||||
CLR_INT (DLI); /* all clr? */
|
||||
else SET_INT (DLI); /* no, set intr */
|
||||
return;
|
||||
}
|
||||
|
||||
void ttix_set_int (int32 ln)
|
||||
void dli_set_int (int32 ln, uint32 wd)
|
||||
{
|
||||
ttix_ireq |= (1 << ln); /* clr mux rcv int */
|
||||
SET_INT (TTIX); /* set master intr */
|
||||
dli_ireq[wd] |= (1 << ln); /* set rcv/dset int */
|
||||
SET_INT (DLI); /* set master intr */
|
||||
return;
|
||||
}
|
||||
|
||||
int32 ttix_iack (void)
|
||||
int32 dli_iack (void)
|
||||
{
|
||||
int32 ln;
|
||||
|
||||
for (ln = 0; ln < TTX_LINES; ln++) { /* find 1st line */
|
||||
if (ttix_ireq & (1 << ln)) {
|
||||
ttix_clr_int (ln); /* clear intr */
|
||||
return (ttix_dib.vec + (ln * 010)); /* return vector */
|
||||
for (ln = 0; ln < DLX_LINES; ln++) { /* find 1st line */
|
||||
if ((dli_ireq[DLI_RCI] | dli_ireq[DLI_DSI]) & (1 << ln)) {
|
||||
dli_clr_int (ln, DLI_RCI); /* clr both req */
|
||||
dli_clr_int (ln, DLI_DSI);
|
||||
return (dli_dib.vec + (ln * 010)); /* return vector */
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void ttox_clr_int (int32 ln)
|
||||
void dlo_clr_int (int32 ln)
|
||||
{
|
||||
ttox_ireq &= ~(1 << ln); /* clr mux rcv int */
|
||||
if (ttox_ireq == 0) CLR_INT (TTOX); /* all clr? */
|
||||
else SET_INT (TTOX); /* no, set intr */
|
||||
dlo_ireq &= ~(1 << ln); /* clr xmit int */
|
||||
if (dlo_ireq == 0) CLR_INT (DLO); /* all clr? */
|
||||
else SET_INT (DLO); /* no, set intr */
|
||||
return;
|
||||
}
|
||||
|
||||
void ttox_set_int (int32 ln)
|
||||
void dlo_set_int (int32 ln)
|
||||
{
|
||||
ttox_ireq |= (1 << ln); /* clr mux rcv int */
|
||||
SET_INT (TTOX); /* set master intr */
|
||||
dlo_ireq |= (1 << ln); /* set xmit int */
|
||||
SET_INT (DLO); /* set master intr */
|
||||
return;
|
||||
}
|
||||
|
||||
int32 ttox_iack (void)
|
||||
int32 dlo_iack (void)
|
||||
{
|
||||
int32 ln;
|
||||
|
||||
for (ln = 0; ln < TTX_LINES; ln++) { /* find 1st line */
|
||||
if (ttox_ireq & (1 << ln)) {
|
||||
ttox_clr_int (ln); /* clear intr */
|
||||
return (ttix_dib.vec + (ln * 010) + 4); /* return vector */
|
||||
for (ln = 0; ln < DLX_LINES; ln++) { /* find 1st line */
|
||||
if (dlo_ireq & (1 << ln)) {
|
||||
dlo_clr_int (ln); /* clear intr */
|
||||
return (dli_dib.vec + (ln * 010) + 4); /* return vector */
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
@@ -372,40 +453,43 @@ return 0;
|
||||
|
||||
/* Reset */
|
||||
|
||||
t_stat ttx_reset (DEVICE *dptr)
|
||||
t_stat dlx_reset (DEVICE *dptr)
|
||||
{
|
||||
int32 ln;
|
||||
|
||||
ttx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
|
||||
sim_cancel (&ttix_unit); /* assume stop */
|
||||
if (ttix_unit.flags & UNIT_ATT) /* if attached, */
|
||||
sim_activate (&ttix_unit, tmxr_poll); /* activate */
|
||||
for (ln = 0; ln < TTX_LINES; ln++) /* for all lines */
|
||||
ttx_reset_ln (ln);
|
||||
return auto_config (ttix_dev.name, ttx_desc.lines); /* auto config */
|
||||
dlx_enbdis (dptr->flags & DEV_DIS); /* sync enables */
|
||||
sim_cancel (&dli_unit); /* assume stop */
|
||||
if (dli_unit.flags & UNIT_ATT) /* if attached, */
|
||||
sim_activate (&dli_unit, tmxr_poll); /* activate */
|
||||
for (ln = 0; ln < DLX_LINES; ln++) /* for all lines */
|
||||
dlx_reset_ln (ln);
|
||||
return auto_config (dli_dev.name, dlx_desc.lines); /* auto config */
|
||||
}
|
||||
|
||||
/* Reset individual line */
|
||||
|
||||
void ttx_reset_ln (uint32 ln)
|
||||
void dlx_reset_ln (int32 ln)
|
||||
{
|
||||
ttix_buf[ln] = 0; /* clear buf, */
|
||||
ttix_csr[ln] = CSR_DONE;
|
||||
ttox_buf[ln] = 0; /* clear buf */
|
||||
ttox_csr[ln] = CSR_DONE;
|
||||
sim_cancel (&ttox_unit[ln]); /* deactivate */
|
||||
ttix_clr_int (ln);
|
||||
ttox_clr_int (ln);
|
||||
dli_buf[ln] = 0; /* clear buf */
|
||||
if (dlo_unit[ln].flags & DLX_MDM) /* modem */
|
||||
dli_csr[ln] &= DLICSR_DTR; /* dont clr DTR */
|
||||
else dli_csr[ln] = 0;
|
||||
dlo_buf[ln] = 0; /* clear buf */
|
||||
dlo_csr[ln] = CSR_DONE;
|
||||
sim_cancel (&dlo_unit[ln]); /* deactivate */
|
||||
dli_clr_int (ln, DLI_RCI);
|
||||
dli_clr_int (ln, DLI_DSI);
|
||||
dlo_clr_int (ln);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Attach master unit */
|
||||
|
||||
t_stat ttx_attach (UNIT *uptr, char *cptr)
|
||||
t_stat dlx_attach (UNIT *uptr, char *cptr)
|
||||
{
|
||||
t_stat r;
|
||||
|
||||
r = tmxr_attach (&ttx_desc, uptr, cptr); /* attach */
|
||||
r = tmxr_attach (&dlx_desc, uptr, cptr); /* attach */
|
||||
if (r != SCPE_OK) return r; /* error */
|
||||
sim_activate (uptr, tmxr_poll); /* start poll */
|
||||
return SCPE_OK;
|
||||
@@ -413,25 +497,25 @@ return SCPE_OK;
|
||||
|
||||
/* Detach master unit */
|
||||
|
||||
t_stat ttx_detach (UNIT *uptr)
|
||||
t_stat dlx_detach (UNIT *uptr)
|
||||
{
|
||||
int32 i;
|
||||
t_stat r;
|
||||
|
||||
r = tmxr_detach (&ttx_desc, uptr); /* detach */
|
||||
for (i = 0; i < TTX_LINES; i++) /* all lines, */
|
||||
ttx_ldsc[i].rcve = 0; /* disable rcv */
|
||||
r = tmxr_detach (&dlx_desc, uptr); /* detach */
|
||||
for (i = 0; i < DLX_LINES; i++) /* all lines, */
|
||||
dlx_ldsc[i].rcve = 0; /* disable rcv */
|
||||
sim_cancel (uptr); /* stop poll */
|
||||
return r;
|
||||
}
|
||||
|
||||
/* Show summary processor */
|
||||
|
||||
t_stat ttx_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
t_stat dlx_summ (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
int32 i, t;
|
||||
|
||||
for (i = t = 0; i < TTX_LINES; i++) t = t + (ttx_ldsc[i].conn != 0);
|
||||
for (i = t = 0; i < DLX_LINES; i++) t = t + (dlx_ldsc[i].conn != 0);
|
||||
if (t == 1) fprintf (st, "1 connection");
|
||||
else fprintf (st, "%d connections", t);
|
||||
return SCPE_OK;
|
||||
@@ -439,16 +523,16 @@ return SCPE_OK;
|
||||
|
||||
/* SHOW CONN/STAT processor */
|
||||
|
||||
t_stat ttx_show (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
t_stat dlx_show (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
int32 i, t;
|
||||
|
||||
for (i = t = 0; i < TTX_LINES; i++) t = t + (ttx_ldsc[i].conn != 0);
|
||||
for (i = t = 0; i < DLX_LINES; i++) t = t + (dlx_ldsc[i].conn != 0);
|
||||
if (t) {
|
||||
for (i = 0; i < TTX_LINES; i++) {
|
||||
if (ttx_ldsc[i].conn) {
|
||||
if (val) tmxr_fconns (st, &ttx_ldsc[i], i);
|
||||
else tmxr_fstats (st, &ttx_ldsc[i], i);
|
||||
for (i = 0; i < DLX_LINES; i++) {
|
||||
if (dlx_ldsc[i].conn) {
|
||||
if (val) tmxr_fconns (st, &dlx_ldsc[i], i);
|
||||
else tmxr_fstats (st, &dlx_ldsc[i], i);
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -458,64 +542,65 @@ return SCPE_OK;
|
||||
|
||||
/* Enable/disable device */
|
||||
|
||||
void ttx_enbdis (int32 dis)
|
||||
void dlx_enbdis (int32 dis)
|
||||
{
|
||||
if (dis) {
|
||||
ttix_dev.flags = ttox_dev.flags | DEV_DIS;
|
||||
ttox_dev.flags = ttox_dev.flags | DEV_DIS;
|
||||
dli_dev.flags = dlo_dev.flags | DEV_DIS;
|
||||
dlo_dev.flags = dlo_dev.flags | DEV_DIS;
|
||||
}
|
||||
else {
|
||||
ttix_dev.flags = ttix_dev.flags & ~DEV_DIS;
|
||||
ttox_dev.flags = ttox_dev.flags & ~DEV_DIS;
|
||||
dli_dev.flags = dli_dev.flags & ~DEV_DIS;
|
||||
dlo_dev.flags = dlo_dev.flags & ~DEV_DIS;
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
/* SHOW VECTOR processor */
|
||||
|
||||
t_stat ttx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
t_stat dlx_show_vec (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
return show_vec (st, uptr, ttx_desc.lines * 2, desc);
|
||||
return show_vec (st, uptr, dlx_desc.lines * 2, desc);
|
||||
}
|
||||
|
||||
/* Change number of lines */
|
||||
|
||||
t_stat ttx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
t_stat dlx_set_lines (UNIT *uptr, int32 val, char *cptr, void *desc)
|
||||
{
|
||||
int32 newln, i, t;
|
||||
t_stat r;
|
||||
|
||||
if (cptr == NULL) return SCPE_ARG;
|
||||
newln = get_uint (cptr, 10, TTX_LINES, &r);
|
||||
if ((r != SCPE_OK) || (newln == ttx_desc.lines)) return r;
|
||||
newln = get_uint (cptr, 10, DLX_LINES, &r);
|
||||
if ((r != SCPE_OK) || (newln == dlx_desc.lines)) return r;
|
||||
if (newln == 0) return SCPE_ARG;
|
||||
if (newln < ttx_desc.lines) {
|
||||
for (i = newln, t = 0; i < ttx_desc.lines; i++) t = t | ttx_ldsc[i].conn;
|
||||
if (newln < dlx_desc.lines) {
|
||||
for (i = newln, t = 0; i < dlx_desc.lines; i++) t = t | dlx_ldsc[i].conn;
|
||||
if (t && !get_yn ("This will disconnect users; proceed [N]?", FALSE))
|
||||
return SCPE_OK;
|
||||
for (i = newln; i < ttx_desc.lines; i++) {
|
||||
if (ttx_ldsc[i].conn) {
|
||||
tmxr_linemsg (&ttx_ldsc[i], "\r\nOperator disconnected line\r\n");
|
||||
tmxr_reset_ln (&ttx_ldsc[i]); /* reset line */
|
||||
for (i = newln; i < dlx_desc.lines; i++) {
|
||||
if (dlx_ldsc[i].conn) {
|
||||
tmxr_linemsg (&dlx_ldsc[i], "\r\nOperator disconnected line\r\n");
|
||||
tmxr_reset_ln (&dlx_ldsc[i]); /* reset line */
|
||||
}
|
||||
ttox_unit[i].flags |= UNIT_DIS;
|
||||
ttx_reset_ln (i);
|
||||
dlo_unit[i].flags |= UNIT_DIS;
|
||||
dlx_reset_ln (i);
|
||||
}
|
||||
}
|
||||
else {
|
||||
for (i = ttx_desc.lines; i < newln; i++) {
|
||||
ttox_unit[i].flags &= ~UNIT_DIS;
|
||||
ttx_reset_ln (i);
|
||||
for (i = dlx_desc.lines; i < newln; i++) {
|
||||
dlo_unit[i].flags &= ~UNIT_DIS;
|
||||
dlx_reset_ln (i);
|
||||
}
|
||||
}
|
||||
ttx_desc.lines = newln;
|
||||
return auto_config (ttix_dev.name, newln); /* auto config */
|
||||
dlx_desc.lines = newln;
|
||||
dli_dib.lnt = newln * 010; /* upd IO page lnt */
|
||||
return auto_config (dli_dev.name, newln); /* auto config */
|
||||
}
|
||||
|
||||
/* Show number of lines */
|
||||
|
||||
t_stat ttx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
t_stat dlx_show_lines (FILE *st, UNIT *uptr, int32 val, void *desc)
|
||||
{
|
||||
fprintf (st, "lines=%d", ttx_desc.lines);
|
||||
fprintf (st, "lines=%d", dlx_desc.lines);
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user