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H316, I7094, NOVA, PDP1, PDP10, PDP8, SDS: Coverity singleton errors

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Most history routines defined a local sim_eval of the proper length, but the
erroneous ones were fixed length machines that defined an integer variable
instead of an integer array of length 1. The VAX used the global sim_eval.
The changes follow the VAX practice.
This commit is contained in:
Bob Supnik 2017-09-07 09:59:04 -07:00 committed by Mark Pizzolato
parent e9d5e2e3c9
commit 5b5e0f9c35
7 changed files with 26 additions and 27 deletions
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8
H316/h316_cpu.c
View File

@ -1,6 +1,6 @@
/* h316_cpu.c: Honeywell 316/516 CPU simulator
Copyright (c) 1999-2015, Robert M. Supnik
Copyright (c) 1999-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
cpu H316/H516 CPU
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
21-May-13 RLA Add IMP/TIP support
Move SMK/OTK instructions here (from CLK)
Make SET CPU DMA work as documented
@ -1757,7 +1758,6 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
{
int32 cr, k, di, op, lnt;
const char *cptr = (const char *) desc;
t_value sim_eval;
t_stat r;
InstHistory *h;
static uint8 has_opnd[16] = {
@ -1786,8 +1786,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->pc & HIST_EA)
fprintf (st, "%05o ", h->ea);
else fprintf (st, " ");
sim_eval = h->ir;
if ((fprint_sym (st, h->pc & X_AMASK, &sim_eval,
sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & X_AMASK, sim_eval,
&cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %06o", h->ir);
op = I_GETOP (h->ir) & 017; /* base op */

10
I7094/i7094_cpu.c
View File

@ -1,6 +1,6 @@
/* i7094_cpu.c: IBM 7094 CPU simulator
Copyright (c) 2003-2011, Robert M. Supnik
Copyright (c) 2003-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
cpu 7094 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
31-Dec-11 RMS Select traps have priority over protect traps
Added SRI, SPI
Fixed user mode and relocation from CTSS RPQ documentation
@ -2400,9 +2401,8 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea,
t_uint64 ir, t_uint64 ac, t_uint64 mq, t_uint64 si, t_uint64 opnd)
{
int32 ch;
t_value sim_eval;
sim_eval = ir;
sim_eval[0] = ir;
if (pc & HIST_PC) { /* instruction? */
fputs ("CPU ", st);
fprintf (st, "%05o ", (int)(pc & AMASK));
@ -2420,7 +2420,7 @@ if (pc & HIST_PC) { /* instruction? */
if (ir & INST_T_DEC)
fprintf (st, " ");
else fprintf (st, "%05o ", ea);
if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M')) > 0) {
if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M')) > 0) {
fputs ("(undefined) ", st);
fprint_val (st, ir, 8, 36, PV_RZRO);
}
@ -2436,7 +2436,7 @@ else if ((ch = HIST_CH (pc))) { /* channel? */
fprintf (st, "%05o ", (int)(pc & AMASK));
fputs (" ", st);
fprintf (st, "%05o ", (int)(ea & AMASK));
if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit,
if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit,
(ch_dev[ch - 1].flags & DEV_7909)? SWMASK ('N'): SWMASK ('I')) > 0) {
fputs ("(undefined) ", st);
fprint_val (st, ir, 8, 36, PV_RZRO);

9
NOVA/nova_cpu.c
View File

@ -1,6 +1,6 @@
/* nova_cpu.c: NOVA CPU simulator
Copyright (c) 1993-2013, Robert M. Supnik
Copyright (c) 1993-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
cpu Nova central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
17-Mar-13 RMS Added clarifying brances to IND_STEP macro (Dave Bryan)
04-Jul-07 BKR DEV_SET/CLR macros now used,
support for non-existant devices added
@ -1372,8 +1373,6 @@ return ( SCPE_OK ) ;
int hist_fprintf( FILE * fp, int itemNum, Hist_entry * hptr )
{
t_value sim_eval ;
if ( hptr )
{
if ( itemNum == 0 )
@ -1394,8 +1393,8 @@ if ( hptr )
fprintf( fp, "%06o %06o ", SP, FP ) ;
}
sim_eval = (hptr->ir & 0xFFFF) ;
if ( (fprint_sym(fp, (hptr->pc & AMASK), &sim_eval, &cpu_unit, SWMASK ('M'))) > 0 )
sim_eval[0] = (hptr->ir & 0xFFFF) ;
if ( (fprint_sym(fp, (hptr->pc & AMASK), sim_eval, &cpu_unit, SWMASK ('M'))) > 0 )
{
fprintf( fp, "(undefined) %04o", (hptr->ir & 0xFFFF) ) ;
}

8
PDP1/pdp1_cpu.c
View File

@ -1,6 +1,6 @@
/* pdp1_cpu.c: PDP-1 CPU simulator
Copyright (c) 1993-2015, Robert M. Supnik
Copyright (c) 1993-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
@ -25,6 +25,7 @@
cpu PDP-1 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
27-Mar-15 RMS Backported changes from GitHub master
21-Mar-12 RMS Fixed & vs && in Ea_ch (Michael Bloom)
30-May-07 RMS Fixed typo in SBS clear (Norm Lastovica)
@ -1665,7 +1666,6 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
int32 ov, pf, op, k, di, lnt;
const char *cptr = (const char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
if (hst_lnt == 0) /* enabled? */
@ -1691,8 +1691,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if ((op < 032) && (op != 007)) /* mem ref instr */
fprintf (st, "%06o ", h->ea);
else fprintf (st, " ");
sim_eval = h->ir;
if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %06o", h->ir);
else if (op < 030) /* mem ref instr */
fprintf (st, " [%06o]", h->opnd);

6
PDP10/pdp10_cpu.c
View File

@ -25,6 +25,7 @@
cpu KS10 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
14-Jan-17 RMS Fixed bugs in 1-proceed
09-Feb-16 RMS Fixed nested indirects and executes (Tim Litt)
25-Mar-12 RMS Added missing parameters to prototypes (Mark Pizzolato)
@ -2528,7 +2529,6 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
int32 k, di, lnt;
const char *cptr = (const char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
if (hst_lnt == 0) /* enabled? */
@ -2550,8 +2550,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
fprint_val (st, h->ac, 8, 36, PV_RZRO);
fputs (" ", st);
fprintf (st, "%06o ", h->ea);
sim_eval = h->ir;
if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) {
sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) {
fputs ("(undefined) ", st);
fprint_val (st, h->ir, 8, 36, PV_RZRO);
}

6
PDP8/pdp8_cpu.c
View File

@ -25,6 +25,7 @@
cpu central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY)
13-Feb-17 RMS RESET clear L'AC, per schematics
28-Jan-17 RMS Renamed switch register variable to SR, per request
@ -1576,7 +1577,6 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
int32 l, k, di, lnt;
const char *cptr = (const char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
if (hst_lnt == 0) /* enabled? */
@ -1599,8 +1599,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->ir < 06000)
fprintf (st, "%05o ", h->ea);
else fprintf (st, " ");
sim_eval = h->ir;
if ((fprint_sym (st, h->pc & ADDRMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & ADDRMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %04o", h->ir);
if (h->ir < 04000)
fprintf (st, " [%04o]", h->opnd);

6
SDS/sds_cpu.c
View File

@ -26,6 +26,7 @@
cpu central processor
rtc real time clock
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
09-Mar-17 RMS trap_P not set if mem mgt trap during fetch (COVERITY)
28-Apr-07 RMS Removed clock initialization
29-Dec-06 RMS Fixed breakpoint variable declarations
@ -1865,7 +1866,6 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, CONST void *desc)
int32 ov, k, di, lnt;
const char *cptr = (const char *) desc;
t_stat r;
t_value sim_eval;
InstHistory *h;
static const char *cyc[] = { " ", " ", "INT", "TRP" };
static const char *modes = "NMU?";
@ -1891,8 +1891,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->ea & HIST_NOEA)
fprintf (st, " ");
else fprintf (st, "%05o ", h->ea);
sim_eval = h->ir;
if ((fprint_sym (st, h->pc, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %08o", h->ir);
fputc ('\n', st); /* end line */
} /* end else instruction */