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Merge branch 'master' into AsyncTmxr

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Conflicts merged and missing changes in new modules added as needed for clock co-scheduling.
This commit is contained in:
Mark Pizzolato
2013-01-21 16:52:42 -08:00
parent 7c7df669ad 95033cee15
commit 83c1d80194
344 changed files with 64292 additions and 11863 deletions
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8
Interdata/id16_cpu.c
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@@ -223,11 +223,6 @@ InstHistory *hst = NULL; /* instruction history *
struct BlockIO blk_io; /* block I/O status */
uint32 (*dev_tab[DEVNO])(uint32 dev, uint32 op, uint32 datout) = { NULL };
extern int32 sim_interval;
extern int32 sim_int_char;
extern uint32 sim_brk_types, sim_brk_dflt, sim_brk_summ; /* breakpoint info */
extern t_bool sim_idle_enab;
uint32 ReadB (uint32 loc);
uint32 ReadH (uint32 loc);
void WriteB (uint32 loc, uint32 val);
@@ -651,7 +646,6 @@ while (reason == 0) { /* loop until halted */
if (PSW & PSW_WAIT) { /* wait state? */
sim_idle (TMR_LFC, TRUE); /* idling */
else sim_interval = sim_interval - 1; /* no, count cycle */
continue;
}
@@ -2010,8 +2004,6 @@ char *cptr = (char *) desc;
t_value sim_eval[2];
t_stat r;
InstHistory *h;
extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
UNIT *uptr, int32 sw);
if (hst_lnt == 0) /* enabled? */
return SCPE_NOFNC;