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Intel-Systems: Reorganize for clean builds with Release targets.
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@@ -45,7 +45,7 @@ void put_mword(uint16 addr, uint16 val);
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extern t_stat i8080_reset (DEVICE *dptr); /* reset the 8080 emulator */
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extern uint8 multibus_get_mbyte(uint16 addr);
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extern void multibus_put_mbyte(uint16 addr, uint8 val);
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extern uint8 EPROM_get_mbyte(uint16 addr);
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extern uint8 EPROM_get_mbyte(uint16 addr, uint8 devnum);
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extern uint8 RAM_get_mbyte(uint16 addr);
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extern void RAM_put_mbyte(uint16 addr, uint8 val);
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extern t_stat i8251_cfg(uint8 base, uint8 devnum);
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@@ -63,7 +63,7 @@ extern t_stat ipc_cont_cfg(uint8 base, uint8 devnum);
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extern t_stat ioc_cont_reset(DEVICE *dptr);
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extern t_stat ioc_cont_cfg(uint8 base, uint8 devnum);
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extern uint8 reg_dev(uint8 (*routine)(t_bool, uint8, uint8), uint8, uint8);
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extern t_stat EPROM_cfg(uint16 base, uint16 size);
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extern t_stat EPROM_cfg(uint16 base, uint16 size, uint8 devnum);
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extern t_stat RAM_cfg(uint16 base, uint16 size);
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extern t_stat multibus_cfg();
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@@ -100,7 +100,7 @@ t_stat SBC_config(void)
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i8259_cfg(I8259_BASE_1, 1);
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ipc_cont_cfg(ICONT_BASE, 0);
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ioc_cont_cfg(DBB_BASE, 0);
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EPROM_cfg(ROM_BASE, ROM_SIZE);
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EPROM_cfg(ROM_BASE, ROM_SIZE, 0);
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RAM_cfg(RAM_BASE, RAM_SIZE);
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return SCPE_OK;
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}
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@@ -131,13 +131,13 @@ uint8 get_mbyte(uint16 addr)
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{
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SET_XACK(1); /* set no XACK */
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if (addr >= 0xF800) { //monitor ROM - always there
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return EPROM_get_mbyte(addr - 0xF000); //top half of EPROM
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return EPROM_get_mbyte(addr - 0xF000, 0); //top half of EPROM
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}
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if ((addr < 0x1000) && ((ipc_cont_unit.u3 & 0x04) == 0)) { //startup
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return EPROM_get_mbyte(addr); //top half of EPROM for boot
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return EPROM_get_mbyte(addr, 0); //top half of EPROM for boot
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}
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if ((addr >= 0xE800) && (addr < 0xF000) && ((ipc_cont_unit.u3 & 0x10) == 0)) { //diagnostic ROM
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return EPROM_get_mbyte(addr - 0xE800); //bottom half of EPROM
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return EPROM_get_mbyte(addr - 0xE800, 0); //bottom half of EPROM
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}
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if (addr < 0x8000) { //IPC RAM
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return RAM_get_mbyte(addr);
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