Notes For V3.3

RESTRICTION: The HP DS disk is not debugged.  DO NOT enable this
feature for normal operations.
WARNING: Massive changes in the PDP-11 make all previous SAVEd
file obsolete.  Do not attempt to use a PDP-11 SAVE file from a
prior release with V3.3!

1. New Features in 3.3

1.1 SCP

- Added -p (powerup) qualifier to RESET
- Changed SET <unit> ONLINE/OFFLINE to SET <unit> ENABLED/DISABLED
- Moved SET DEBUG under SET CONSOLE hierarchy
- Added optional parameter value to SHOW command
- Added output file option to SHOW command

1.2 PDP-11

- Separated RH Massbus adapter from RP controller
- Added TU tape support
- Added model emulation framework
- Added model details

1.3 VAX

- Separated out CVAX-specific features from core instruction simulator
- Implemented capability for CIS, octaword, compatibility mode instructions
- Added instruction display and parse for compatibility mode
- Changed SET CPU VIRTUAL=n to SHOW CPU VIRTUAL=n
- Added =n optional parameter to SHOW CPU HISTORY

1.4 Unibus/Qbus simulators (PDP-11, VAX, PDP-10)

- Simplified DMA API's
- Modified DMA peripherals to use simplified API's

1.5 HP2100 (all changes from Dave Bryan)

CPU	- moved MP into its own device; added MP option jumpers
	- modified DMA to allow disabling
	- modified SET CPU 2100/2116 to truncate memory > 32K
	- added -F switch to SET CPU to force memory truncation
	- modified WRU to be REG_HRO
	- added BRK and DEL to save console settings

DR	- provided protected tracks and "Writing Enabled" status bit
	- added "parity error" status return on writes for 12606
	- added track origin test for 12606
	- added SCP test for 12606
	- added "Sector Flag" status bit
	- added "Read Inhibit" status bit for 12606
	- added TRACKPROT modifier

LPS	- added SET OFFLINE/ONLINE, POWEROFF/POWERON
	- added fast/realistic timing
	- added debug printouts

LPT	- added SET OFFLINE/ONLINE, POWEROFF/POWERON

PTR	- added paper tape loop mode, DIAG/READER modifiers to PTR
	- added PV_LEFT to PTR TRLLIM register

CLK	- modified CLK to permit disable

1.6 IBM 1401, IBM 1620, Interdata 16b, SDS 940, PDP-10

- Added instruction history

1.7 H316, PDP-15, PDP-8

- Added =n optional value to SHOW CPU HISTORY

2. Bugs Fixed in 3.3

2.1 SCP

- Fixed comma-separated SET options (from Dave Bryan)
- Fixed duplicate HELP displays with user-specified commands

2.2 PDP-10

- Replicated RP register state per drive
- Fixed TU to set FCE on short record
- Fixed TU to return bit<15> in drive type
- Fixed TU format specification, 1:0 are don't cares
- Fixed TU handling of TMK status
- Fixed TU handling of DONE, ATA at end of operation
- Implemented TU write check

2.3 PDP-11

- Replicated RP register state per drive
- Fixed RQ, TQ to report correct controller type and stage 1 configuration
  flags on a Unibus system
- Fixed HK CS2<output_ready> flag

2.4 VAX

- Fixed parsing of indirect displacement modes in instruction input

2.5 HP2100 (all fixes from Dave Bryan)

CPU	- fixed S-register behavior on 2116
	- fixed LIx/MIx behavior for DMA on 2116 and 2100
	- fixed LIx/MIx behavior for empty I/O card slots

DP	- fixed enable/disable from either device
	- fixed ANY ERROR status for 12557A interface
	- fixed unattached drive status for 12557A interface
	- status cmd without prior STC DC now completes (12557A)
	- OTA/OTB CC on 13210A interface also does CLC CC
	- fixed RAR model
	- fixed seek check on 13210 if sector out of range

DQ	- fixed enable/disable from either device
	- shortened xtime from 5 to 3 (drive avg 156KW/second)
	- fixed not ready/any error status
	- fixed RAR model

DR	- fixed enable/disable from either device
	- fixed sector return in status word
	- fixed DMA last word write, incomplete sector fill value
	- fixed 12610 SFC operation
	- fixed current-sector determination

IPL	- fixed enable/disable from either device

LPS	- fixed status returns for error conditions
	- fixed handling of non-printing characters
	- fixed handling of characters after column 80
	- improved timing model accuracy for RTE

LPT	- fixed status returns for error conditions
	- fixed TOF handling so form remains on line 0

SYS	- fixed display of CCA/CCB/CCE instructions

2.5 PDP-15

FPP	- fixed URFST to mask low 9b of fraction
	- fixed exception PC setting

PDP1/pdp1_cpu.c

@@ -25,6 +25,7 @@
 
    cpu		PDP-1 central processor
 
+   09-Nov-04	RMS	Added instruction history
    07-Sep-03	RMS	Added additional explanation on I/O simulation
    01-Sep-03	RMS	Added address switches for hardware readin
    23-Jul-03	RMS	Revised to detect I/O wait hang
@@ -229,6 +230,18 @@
 #define UNIT_MDV	(1 << UNIT_V_MDV)
 #define UNIT_MSIZE	(1 << UNIT_V_MSIZE)
 
+#define HIST_PC		0x40000000
+#define HIST_V_SHF	18
+#define HIST_MIN	64
+#define HIST_MAX	65536
+struct InstHistory {
+	uint32		pc;
+	uint32		ir;
+	uint32		ovac;
+	uint32		pfio;
+	uint32		ea;
+	uint32		opnd;  };
+
 int32 M[MAXMEMSIZE] = { 0 };				/* memory */
 int32 AC = 0;						/* AC */
 int32 IO = 0;						/* IO */
@@ -252,6 +265,9 @@ int32 ind_max = 16;					/* nested ind limit */
 uint16 pcq[PCQ_SIZE] = { 0 };				/* PC queue */
 int32 pcq_p = 0;					/* PC queue ptr */
 REG *pcq_r = NULL;					/* PC queue reg ptr */
+int32 hst_p = 0;					/* history pointer */
+int32 hst_lnt = 0;					/* history length */
+struct InstHistory *hst = NULL;				/* instruction history */
 
 extern UNIT *sim_clock_queue;
 extern int32 sim_int_char;
@@ -261,6 +277,8 @@ t_stat cpu_ex (t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);
 t_stat cpu_dep (t_value val, t_addr addr, UNIT *uptr, int32 sw);
 t_stat cpu_reset (DEVICE *dptr);
 t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
+t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc);
+t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc);
 
 extern int32 ptr (int32 inst, int32 dev, int32 dat);
 extern int32 ptp (int32 inst, int32 dev, int32 dat);
@@ -355,6 +373,8 @@ MTAB cpu_mod[] = {
 	{ UNIT_MSIZE, 32768, NULL, "32K", &cpu_set_size },
 	{ UNIT_MSIZE, 49152, NULL, "48K", &cpu_set_size },
 	{ UNIT_MSIZE, 65536, NULL, "64K", &cpu_set_size },
+	{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
+	  &cpu_set_hist, &cpu_show_hist },
 	{ 0 }  };
 
 DEVICE cpu_dev = {
@@ -408,6 +428,13 @@ IR = M[MA];						/* fetch instruction */
 PC = INCR_ADDR (PC);					/* increment PC */
 xct_count = 0;						/* track nested XCT's */
 sim_interval = sim_interval - 1;
+if (hst_lnt) {						/* history enabled? */
+	hst_p = (hst_p + 1);				/* next entry */
+	if (hst_p >= hst_lnt) hst_p = 0;
+	hst[hst_p].pc = MA | HIST_PC;			/* save PC, IR, LAC, MQ */
+	hst[hst_p].ir = IR;
+	hst[hst_p].ovac = (OV << HIST_V_SHF) | AC;
+	hst[hst_p].pfio = (PF << HIST_V_SHF) | IO;  }
 
 xct_instr:						/* label for XCT */
 if ((IR == (OP_JMP+IA+1)) && ((MA & EPCMASK) == 0) && (sbs & SB_ON)) {
@@ -430,7 +457,13 @@ if ((op < 032) && (op != 007)) {			/* mem ref instr */
 		    if ((t & IA) == 0) break;  }
 		if (i >= ind_max) {			/* indirect loop? */
 		    reason = STOP_IND;
-		    break;  }  }  }  }
+		    break;  }				/* end if loop */
+		}					/* end else !extm */
+	    }						/* end if indirect */
+	if (hst_p) {					/* history enabled? */
+	    hst[hst_p].ea = MA;
+	    hst[hst_p].opnd = M[MA];  }
+	}
 
 switch (op) {						/* decode IR<0:4> */
 
@@ -852,3 +885,70 @@ MEMSIZE = val;
 for (i = MEMSIZE; i < MAXMEMSIZE; i++) M[i] = 0;
 return SCPE_OK;
 }
+
+/* Set history */
+
+t_stat cpu_set_hist (UNIT *uptr, int32 val, char *cptr, void *desc)
+{
+int32 i, lnt;
+t_stat r;
+
+if (cptr == NULL) {
+	for (i = 0; i < hst_lnt; i++) hst[i].pc = 0;
+	hst_p = 0;
+	return SCPE_OK;  }
+lnt = (int32) get_uint (cptr, 10, HIST_MAX, &r);
+if ((r != SCPE_OK) || (lnt && (lnt < HIST_MIN))) return SCPE_ARG;
+hst_p = 0;
+if (hst_lnt) {
+	free (hst);
+	hst_lnt = 0;
+	hst = NULL;  }
+if (lnt) {
+	hst = calloc (sizeof (struct InstHistory), lnt);
+	if (hst == NULL) return SCPE_MEM;
+	hst_lnt = lnt;  }
+return SCPE_OK;
+}
+
+/* Show history */
+
+t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
+{
+int32 ov, pf, op, k, di, lnt;
+char *cptr = (char *) desc;
+t_stat r;
+t_value sim_eval;
+struct InstHistory *h;
+extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val,
+	UNIT *uptr, int32 sw);
+
+if (hst_lnt == 0) return SCPE_NOFNC;			/* enabled? */
+if (cptr) {
+	lnt = (int32) get_uint (cptr, 10, hst_lnt, &r);
+	if ((r != SCPE_OK) || (lnt == 0)) return SCPE_ARG;  }
+else lnt = hst_lnt;
+di = hst_p - lnt;					/* work forward */
+if (di < 0) di = di + hst_lnt;
+fprintf (st, "PC      OV AC     IO     PF EA      IR\n\n");
+for (k = 0; k < lnt; k++) {				/* print specified */
+	h = &hst[(++di) % hst_lnt];			/* entry pointer */
+	if (h->pc & HIST_PC) {				/* instruction? */
+	    ov = (h->ovac >> HIST_V_SHF) & 1;		/* overflow */
+	    pf = (h->pfio >> HIST_V_SHF) & 077;		/* prog flags */
+	    op = ((h->ir >> 13) & 037);			/* get opcode */
+	    fprintf (st, "%06o  %o  %06o %06o %02o ",
+		h->pc & AMASK, ov, h->ovac & DMASK, h->pfio & DMASK, pf);
+	    if ((op < 032) && (op != 007))		/* mem ref instr */
+		fprintf (st, "%06o  ", h->ea);
+	    else fprintf (st, "        ");
+	    sim_eval = h->ir;
+	    if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
+		fprintf (st, "(undefined) %06o", h->ir);
+	    else if ((op < 032) && (op != 007))		/* mem ref instr */
+		fprintf (st, " [%06o]", h->opnd);
+	    fputc ('\n', st);				/* end line */
+	    }						/* end else instruction */
+	}						/* end for */
+return SCPE_OK;
+}

PDP1/pdp1_doc.txt

@@ -1,7 +1,7 @@
 To:	Users
 From:	Bob Supnik
 Subj:	PDP-1 Simulator Usage
-Date:	15-Feb-2004
+Date:	15-Nov-2004
 
 			COPYRIGHT NOTICE
 
@@ -150,6 +150,17 @@ control registers for the interrupt system.
 	IND_MAX		8	maximum nested indirect addresses
 	WRU		8	interrupt character
 
+The CPU can maintain a history of the most recently executed instructions.
+This is controlled by the SET CPU HISTORY and SHOW CPU HISTORY commands:
+
+	SET CPU HISTORY		clear history buffer
+	SET CPU HISTORY=0	disable history
+	SET CPU HISTORY=n	enable history, length = n
+	SHOW CPU HISTORY	print CPU history
+	SHOW CPU HISTORY=n	print first n entries of CPU history
+
+The maximum length for the history is 65536 entries.
+
 2.2 Programmed I/O Devices
 
 2.2.1 Paper Tape Reader (PTR)
@@ -280,7 +291,7 @@ locked.
 	SET DTn WRITEENABLED	set unit n write enabled
 	SET DTn LOCKED		set unit n write locked
 
-Units can also be set ONLINE or OFFLINE.
+Units can also be set ENABLED or DISABLED.
 
 The DECtape controller can be disabled and enabled with the SET DT DISABLED
 and SET DT ENABLED commands, respectively.