mirror of
https://github.com/open-simh/simh.git
synced 2026-05-05 15:43:58 +00:00
Notes For V3.5-0
The source set has been extensively overhauled. For correct viewing, set Visual C++ or Emacs to have tab stops every 4 characters. 1. New Features in 3.4-1 1.1 All Ethernet devices - Added Windows user-defined adapter names (from Timothe Litt) 1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors - Added support for SET <unit>n DISCONNECT 1.3 VAX - Added latent QDSS support - Revised autoconfigure to handle QDSS 1.4 PDP-11 - Revised autoconfigure to handle more casees 2. Bugs Fixed in 3.4-1 2.1 SCP and libraries - Trim trailing spaces on all input (for example, attach file names) - Fixed sim_sock spurious SIGPIPE error in Unix/Linux - Fixed sim_tape misallocation of TPC map array for 64b simulators 2.2 1401 - Fixed bug, CPU reset was clearing SSB through SSG 2.3 PDP-11 - Fixed bug in VH vector display routine - Fixed XU runt packet processing (found by Tim Chapman) 2.4 Interdata - Fixed bug in SHOW PAS CONN/STATS - Fixed potential integer overflow exception in divide 2.5 SDS - Fixed bug in SHOW MUX CONN/STATS 2.6 HP - Fixed bug in SHOW MUX CONN/STATS 2.7 PDP-8 - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.8 PDP-18b - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.9 Nova, Eclipse - Fixed potential integer overflow exception in divide
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
ec60bbf329
commit
b7c1eae41f
@@ -1,6 +1,6 @@
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/* pdp11_stddev.c: PDP-11 standard I/O devices simulator
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Copyright (c) 1993-2004, Robert M Supnik
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Copyright (c) 1993-2005, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -19,64 +19,64 @@
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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tti,tto DL11 terminal input/output
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clk KW11L (and other) line frequency clock
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tti,tto DL11 terminal input/output
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clk KW11L (and other) line frequency clock
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11-Oct-04 RMS Added clock model dependencies
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28-May-04 RMS Removed SET TTI CTRL-C
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29-Dec-03 RMS Added console backpressure support
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25-Apr-03 RMS Revised for extended file support
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01-Mar-03 RMS Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C
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22-Nov-02 RMS Changed terminal default to 7B for UNIX
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01-Nov-02 RMS Added 7B/8B support to terminal
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29-Sep-02 RMS Added vector display support
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Split out paper tape
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Split DL11 dibs
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30-May-02 RMS Widened POS to 32b
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26-Jan-02 RMS Revised for multiple timers
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09-Jan-02 RMS Fixed bugs in KW11L (found by John Dundas)
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06-Jan-02 RMS Split I/O address routines, revised enable/disable support
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29-Nov-01 RMS Added read only unit support
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09-Nov-01 RMS Added RQDX3 support
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07-Oct-01 RMS Upgraded clock to full KW11L for RSTS/E autoconfigure
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07-Sep-01 RMS Moved function prototypes, revised interrupt mechanism
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17-Jul-01 RMS Moved function prototype
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04-Jul-01 RMS Added DZ11 support
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05-Mar-01 RMS Added clock calibration support
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30-Oct-00 RMS Standardized register order
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25-Jun-98 RMS Fixed bugs in paper tape error handling
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07-Jul-05 RMS Removed extraneous externs
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11-Oct-04 RMS Added clock model dependencies
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28-May-04 RMS Removed SET TTI CTRL-C
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29-Dec-03 RMS Added console backpressure support
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25-Apr-03 RMS Revised for extended file support
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01-Mar-03 RMS Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C
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22-Nov-02 RMS Changed terminal default to 7B for UNIX
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01-Nov-02 RMS Added 7B/8B support to terminal
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29-Sep-02 RMS Added vector display support
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Split out paper tape
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Split DL11 dibs
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30-May-02 RMS Widened POS to 32b
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26-Jan-02 RMS Revised for multiple timers
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09-Jan-02 RMS Fixed bugs in KW11L (found by John Dundas)
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06-Jan-02 RMS Split I/O address routines, revised enable/disable support
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29-Nov-01 RMS Added read only unit support
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09-Nov-01 RMS Added RQDX3 support
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07-Oct-01 RMS Upgraded clock to full KW11L for RSTS/E autoconfigure
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07-Sep-01 RMS Moved function prototypes, revised interrupt mechanism
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17-Jul-01 RMS Moved function prototype
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04-Jul-01 RMS Added DZ11 support
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05-Mar-01 RMS Added clock calibration support
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30-Oct-00 RMS Standardized register order
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25-Jun-98 RMS Fixed bugs in paper tape error handling
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*/
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#include "pdp11_defs.h"
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_DONE + CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 8000
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#define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */
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#define TTICSR_RW (CSR_IE)
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#define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */
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#define TTOCSR_RW (CSR_IE)
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#define CLKCSR_IMP (CSR_DONE + CSR_IE) /* real-time clock */
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#define CLKCSR_RW (CSR_IE)
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#define CLK_DELAY 8000
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#define UNIT_V_8B (UNIT_V_UF + 0) /* 8B */
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#define UNIT_8B (1 << UNIT_V_8B)
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#define UNIT_V_8B (UNIT_V_UF + 0) /* 8B */
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#define UNIT_8B (1 << UNIT_V_8B)
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extern int32 int_req[IPL_HLVL];
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extern int32 int_vec[IPL_HLVL][32];
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extern int32 cpu_type;
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int32 tti_csr = 0; /* control/status */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 60; /* ticks/second */
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int32 clk_default = 60; /* default ticks/second */
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int32 clk_fie = 0; /* force IE = 1 */
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int32 clk_fnxm = 0; /* force NXM on reg */
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int32 tmxr_poll = CLK_DELAY; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* timer poll */
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int32 tti_csr = 0; /* control/status */
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int32 tto_csr = 0; /* control/status */
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int32 clk_csr = 0; /* control/status */
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int32 clk_tps = 60; /* ticks/second */
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int32 clk_default = 60; /* default ticks/second */
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int32 clk_fie = 0; /* force IE = 1 */
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int32 clk_fnxm = 0; /* force NXM on reg */
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int32 tmxr_poll = CLK_DELAY; /* term mux poll */
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int32 tmr_poll = CLK_DELAY; /* timer poll */
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t_stat tti_rd (int32 *data, int32 PA, int32 access);
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t_stat tti_wr (int32 data, int32 PA, int32 access);
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@@ -94,157 +94,180 @@ int32 clk_inta (void);
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t_stat clk_reset (DEVICE *dptr);
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t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);
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t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);
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/* TTI data structures
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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tti_dev TTI device descriptor
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tti_unit TTI unit descriptor
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tti_reg TTI register list
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*/
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DIB tti_dib = { IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
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1, IVCL (TTI), VEC_TTI, { NULL } };
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DIB tti_dib = {
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IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,
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1, IVCL (TTI), VEC_TTI, { NULL }
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};
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UNIT tti_unit = { UDATA (&tti_svc, 0, 0), KBD_POLL_WAIT };
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REG tti_reg[] = {
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{ ORDATA (BUF, tti_unit.buf, 8) },
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{ ORDATA (CSR, tti_csr, 16) },
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{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
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{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
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{ FLDATA (IE, tti_csr, CSR_V_IE) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL } };
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{ ORDATA (BUF, tti_unit.buf, 8) },
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{ ORDATA (CSR, tti_csr, 16) },
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{ FLDATA (INT, IREQ (TTI), INT_V_TTI) },
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{ FLDATA (ERR, tti_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tti_csr, CSR_V_DONE) },
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{ FLDATA (IE, tti_csr, CSR_V_IE) },
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{ DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tti_unit.wait, 24), REG_NZ + PV_LEFT },
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{ NULL }
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};
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MTAB tti_mod[] = {
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{ UNIT_8B, 0 , "7b" , "7B" , &tty_set_mode },
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{ UNIT_8B, UNIT_8B , "8b" , "8B" , &tty_set_mode },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 } };
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{ UNIT_8B, 0 , "7b" , "7B" , &tty_set_mode },
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{ UNIT_8B, UNIT_8B , "8b" , "8B" , &tty_set_mode },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE tti_dev = {
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, DEV_UBUS | DEV_QBUS };
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"TTI", &tti_unit, tti_reg, tti_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tti_reset,
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NULL, NULL, NULL,
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&tti_dib, DEV_UBUS | DEV_QBUS
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};
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/* TTO data structures
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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tto_dev TTO device descriptor
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tto_unit TTO unit descriptor
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tto_reg TTO register list
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*/
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DIB tto_dib = { IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,
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1, IVCL (TTO), VEC_TTO, { NULL } };
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DIB tto_dib = {
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IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,
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1, IVCL (TTO), VEC_TTO, { NULL }
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};
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UNIT tto_unit = { UDATA (&tto_svc, 0, 0), SERIAL_OUT_WAIT };
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REG tto_reg[] = {
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{ ORDATA (BUF, tto_unit.buf, 8) },
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{ ORDATA (CSR, tto_csr, 16) },
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{ FLDATA (INT, IREQ (TTO), INT_V_TTO) },
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{ FLDATA (ERR, tto_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
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{ FLDATA (IE, tto_csr, CSR_V_IE) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL } };
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{ ORDATA (BUF, tto_unit.buf, 8) },
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{ ORDATA (CSR, tto_csr, 16) },
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{ FLDATA (INT, IREQ (TTO), INT_V_TTO) },
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{ FLDATA (ERR, tto_csr, CSR_V_ERR) },
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{ FLDATA (DONE, tto_csr, CSR_V_DONE) },
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{ FLDATA (IE, tto_csr, CSR_V_IE) },
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{ DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },
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{ DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },
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{ NULL }
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};
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MTAB tto_mod[] = {
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{ UNIT_8B, 0 , "7b" , "7B" , &tty_set_mode },
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{ UNIT_8B, UNIT_8B , "8b" , "8B" , &tty_set_mode },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 } };
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{ UNIT_8B, 0 , "7b" , "7B" , &tty_set_mode },
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{ UNIT_8B, UNIT_8B , "8b" , "8B" , &tty_set_mode },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE tto_dev = {
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, DEV_UBUS | DEV_QBUS };
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"TTO", &tto_unit, tto_reg, tto_mod,
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1, 10, 31, 1, 8, 8,
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NULL, NULL, &tto_reset,
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NULL, NULL, NULL,
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&tto_dib, DEV_UBUS | DEV_QBUS
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};
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/* CLK data structures
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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clk_dev CLK device descriptor
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clk_unit CLK unit descriptor
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clk_reg CLK register list
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*/
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DIB clk_dib = { IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,
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1, IVCL (CLK), VEC_CLK, { &clk_inta } };
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DIB clk_dib = {
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IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,
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1, IVCL (CLK), VEC_CLK, { &clk_inta }
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};
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UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 8000 };
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REG clk_reg[] = {
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{ ORDATA (CSR, clk_csr, 16) },
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{ FLDATA (INT, IREQ (CLK), INT_V_CLK) },
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{ FLDATA (DONE, clk_csr, CSR_V_DONE) },
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{ FLDATA (IE, clk_csr, CSR_V_IE) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 16), PV_LEFT + REG_HRO },
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{ DRDATA (DEFTPS, clk_default, 16), PV_LEFT + REG_HRO },
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{ FLDATA (FIE, clk_fie, 0), REG_HIDDEN },
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{ FLDATA (FNXM, clk_fnxm, 0), REG_HIDDEN },
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{ NULL } };
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{ ORDATA (CSR, clk_csr, 16) },
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{ FLDATA (INT, IREQ (CLK), INT_V_CLK) },
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{ FLDATA (DONE, clk_csr, CSR_V_DONE) },
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{ FLDATA (IE, clk_csr, CSR_V_IE) },
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{ DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },
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{ DRDATA (TPS, clk_tps, 16), PV_LEFT + REG_HRO },
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{ DRDATA (DEFTPS, clk_default, 16), PV_LEFT + REG_HRO },
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{ FLDATA (FIE, clk_fie, 0), REG_HIDDEN },
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{ FLDATA (FNXM, clk_fnxm, 0), REG_HIDDEN },
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{ NULL }
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};
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MTAB clk_mod[] = {
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{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
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NULL, &clk_show_freq, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 } };
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{ MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",
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&clk_set_freq, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,
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NULL, &clk_show_freq, NULL },
|
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{ MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,
|
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NULL, &show_addr, NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,
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NULL, &show_vec, NULL },
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{ 0 }
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};
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DEVICE clk_dev = {
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
|
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NULL, NULL, &clk_reset,
|
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NULL, NULL, NULL,
|
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&clk_dib, DEV_UBUS | DEV_QBUS };
|
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|
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"CLK", &clk_unit, clk_reg, clk_mod,
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1, 0, 0, 0, 0, 0,
|
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NULL, NULL, &clk_reset,
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NULL, NULL, NULL,
|
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&clk_dib, DEV_UBUS | DEV_QBUS
|
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};
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|
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/* Terminal input address routines */
|
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t_stat tti_rd (int32 *data, int32 PA, int32 access)
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{
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switch ((PA >> 1) & 01) { /* decode PA<1> */
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case 00: /* tti csr */
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*data = tti_csr & TTICSR_IMP;
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return SCPE_OK;
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case 01: /* tti buf */
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tti_csr = tti_csr & ~CSR_DONE;
|
||||
CLR_INT (TTI);
|
||||
*data = tti_unit.buf & 0377;
|
||||
return SCPE_OK; } /* end switch PA */
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
|
||||
case 00: /* tti csr */
|
||||
*data = tti_csr & TTICSR_IMP;
|
||||
return SCPE_OK;
|
||||
|
||||
case 01: /* tti buf */
|
||||
tti_csr = tti_csr & ~CSR_DONE;
|
||||
CLR_INT (TTI);
|
||||
*data = tti_unit.buf & 0377;
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
t_stat tti_wr (int32 data, int32 PA, int32 access)
|
||||
{
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
case 00: /* tti csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if ((data & CSR_IE) == 0) CLR_INT (TTI);
|
||||
else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
SET_INT (TTI);
|
||||
tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
|
||||
return SCPE_OK;
|
||||
case 01: /* tti buf */
|
||||
return SCPE_OK; } /* end switch PA */
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
|
||||
case 00: /* tti csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if ((data & CSR_IE) == 0) CLR_INT (TTI);
|
||||
else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
SET_INT (TTI);
|
||||
tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);
|
||||
return SCPE_OK;
|
||||
|
||||
case 01: /* tti buf */
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
@@ -254,9 +277,9 @@ t_stat tti_svc (UNIT *uptr)
|
||||
{
|
||||
int32 c;
|
||||
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
|
||||
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
|
||||
if (c & SCPE_BREAK) tti_unit.buf = 0; /* break? */
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* continue poll */
|
||||
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */
|
||||
if (c & SCPE_BREAK) tti_unit.buf = 0; /* break? */
|
||||
else tti_unit.buf = c & ((tti_unit.flags & UNIT_8B)? 0377: 0177);
|
||||
tti_unit.pos = tti_unit.pos + 1;
|
||||
tti_csr = tti_csr | CSR_DONE;
|
||||
@@ -271,40 +294,48 @@ t_stat tti_reset (DEVICE *dptr)
|
||||
tti_unit.buf = 0;
|
||||
tti_csr = 0;
|
||||
CLR_INT (TTI);
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
|
||||
sim_activate (&tti_unit, tti_unit.wait); /* activate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* Terminal output address routines */
|
||||
|
||||
t_stat tto_rd (int32 *data, int32 PA, int32 access)
|
||||
{
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
case 00: /* tto csr */
|
||||
*data = tto_csr & TTOCSR_IMP;
|
||||
return SCPE_OK;
|
||||
case 01: /* tto buf */
|
||||
*data = tto_unit.buf;
|
||||
return SCPE_OK; } /* end switch PA */
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
|
||||
case 00: /* tto csr */
|
||||
*data = tto_csr & TTOCSR_IMP;
|
||||
return SCPE_OK;
|
||||
|
||||
case 01: /* tto buf */
|
||||
*data = tto_unit.buf;
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
t_stat tto_wr (int32 data, int32 PA, int32 access)
|
||||
{
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
case 00: /* tto csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if ((data & CSR_IE) == 0) CLR_INT (TTO);
|
||||
else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
SET_INT (TTO);
|
||||
tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
|
||||
return SCPE_OK;
|
||||
case 01: /* tto buf */
|
||||
if ((PA & 1) == 0) tto_unit.buf = data & 0377;
|
||||
tto_csr = tto_csr & ~CSR_DONE;
|
||||
CLR_INT (TTO);
|
||||
sim_activate (&tto_unit, tto_unit.wait);
|
||||
return SCPE_OK; } /* end switch PA */
|
||||
switch ((PA >> 1) & 01) { /* decode PA<1> */
|
||||
|
||||
case 00: /* tto csr */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
if ((data & CSR_IE) == 0) CLR_INT (TTO);
|
||||
else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)
|
||||
SET_INT (TTO);
|
||||
tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);
|
||||
return SCPE_OK;
|
||||
|
||||
case 01: /* tto buf */
|
||||
if ((PA & 1) == 0) tto_unit.buf = data & 0377;
|
||||
tto_csr = tto_csr & ~CSR_DONE;
|
||||
CLR_INT (TTO);
|
||||
sim_activate (&tto_unit, tto_unit.wait);
|
||||
return SCPE_OK;
|
||||
} /* end switch PA */
|
||||
|
||||
return SCPE_NXM;
|
||||
}
|
||||
|
||||
@@ -316,9 +347,10 @@ int32 c;
|
||||
t_stat r;
|
||||
|
||||
c = tto_unit.buf & ((tto_unit.flags & UNIT_8B)? 0377: 0177);
|
||||
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
|
||||
sim_activate (uptr, uptr->wait); /* try again */
|
||||
return ((r == SCPE_STALL)? SCPE_OK: r); } /* !stall? report */
|
||||
if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */
|
||||
sim_activate (uptr, uptr->wait); /* try again */
|
||||
return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */
|
||||
}
|
||||
tto_csr = tto_csr | CSR_DONE;
|
||||
if (tto_csr & CSR_IE) SET_INT (TTO);
|
||||
tto_unit.pos = tto_unit.pos + 1;
|
||||
@@ -332,7 +364,7 @@ t_stat tto_reset (DEVICE *dptr)
|
||||
tto_unit.buf = 0;
|
||||
tto_csr = CSR_DONE;
|
||||
CLR_INT (TTO);
|
||||
sim_cancel (&tto_unit); /* deactivate unit */
|
||||
sim_cancel (&tto_unit); /* deactivate unit */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -342,34 +374,34 @@ tti_unit.flags = (tti_unit.flags & ~UNIT_8B) | val;
|
||||
tto_unit.flags = (tto_unit.flags & ~UNIT_8B) | val;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* The line time clock has a few twists and turns through the history of 11's
|
||||
|
||||
LSI-11 no CSR
|
||||
LSI-11/23 (KDF11A) no CSR
|
||||
PDP-11/23+ (KDF11B) no monitor bit
|
||||
PDP-11/24 (KDF11U) monitor bit clears on IAK
|
||||
LSI-11 no CSR
|
||||
LSI-11/23 (KDF11A) no CSR
|
||||
PDP-11/23+ (KDF11B) no monitor bit
|
||||
PDP-11/24 (KDF11U) monitor bit clears on IAK
|
||||
*/
|
||||
|
||||
/* Clock I/O address routines */
|
||||
|
||||
t_stat clk_rd (int32 *data, int32 PA, int32 access)
|
||||
{
|
||||
if (clk_fnxm) return SCPE_NXM; /* not there??? */
|
||||
if (CPUT (HAS_LTCM)) *data = clk_csr & CLKCSR_IMP; /* monitor bit? */
|
||||
else *data = clk_csr & (CLKCSR_IMP & ~CSR_DONE); /* no, just IE */
|
||||
if (clk_fnxm) return SCPE_NXM; /* not there??? */
|
||||
if (CPUT (HAS_LTCM)) *data = clk_csr & CLKCSR_IMP; /* monitor bit? */
|
||||
else *data = clk_csr & (CLKCSR_IMP & ~CSR_DONE); /* no, just IE */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
t_stat clk_wr (int32 data, int32 PA, int32 access)
|
||||
{
|
||||
if (clk_fnxm) return SCPE_NXM; /* not there??? */
|
||||
if (clk_fnxm) return SCPE_NXM; /* not there??? */
|
||||
if (PA & 1) return SCPE_OK;
|
||||
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);
|
||||
if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0)) /* monitor bit? */
|
||||
clk_csr = clk_csr & ~CSR_DONE; /* clr if zero */
|
||||
if ((((clk_csr & CSR_IE) == 0) && !clk_fie) || /* unless IE+DONE */
|
||||
((clk_csr & CSR_DONE) == 0)) CLR_INT (CLK); /* clr intr */
|
||||
if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0)) /* monitor bit? */
|
||||
clk_csr = clk_csr & ~CSR_DONE; /* clr if zero */
|
||||
if ((((clk_csr & CSR_IE) == 0) && !clk_fie) || /* unless IE+DONE */
|
||||
((clk_csr & CSR_DONE) == 0)) CLR_INT (CLK); /* clr intr */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -379,12 +411,12 @@ t_stat clk_svc (UNIT *uptr)
|
||||
{
|
||||
int32 t;
|
||||
|
||||
clk_csr = clk_csr | CSR_DONE; /* set done */
|
||||
clk_csr = clk_csr | CSR_DONE; /* set done */
|
||||
if ((clk_csr & CSR_IE) || clk_fie) SET_INT (CLK);
|
||||
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
|
||||
sim_activate (&clk_unit, t); /* reactivate unit */
|
||||
tmr_poll = t; /* set timer poll */
|
||||
tmxr_poll = t; /* set mux poll */
|
||||
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
|
||||
sim_activate (&clk_unit, t); /* reactivate unit */
|
||||
tmr_poll = t; /* set timer poll */
|
||||
tmxr_poll = t; /* set mux poll */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -400,14 +432,14 @@ return clk_dib.vec;
|
||||
|
||||
t_stat clk_reset (DEVICE *dptr)
|
||||
{
|
||||
if (CPUT (HAS_LTCR)) clk_fie = clk_fnxm = 0; /* reg there? */
|
||||
else clk_fie = clk_fnxm = 1; /* no, BEVENT */
|
||||
clk_tps = clk_default; /* set default tps */
|
||||
clk_csr = CSR_DONE; /* set done */
|
||||
if (CPUT (HAS_LTCR)) clk_fie = clk_fnxm = 0; /* reg there? */
|
||||
else clk_fie = clk_fnxm = 1; /* no, BEVENT */
|
||||
clk_tps = clk_default; /* set default tps */
|
||||
clk_csr = CSR_DONE; /* set done */
|
||||
CLR_INT (CLK);
|
||||
sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
|
||||
tmr_poll = clk_unit.wait; /* set timer poll */
|
||||
tmxr_poll = clk_unit.wait; /* set mux poll */
|
||||
sim_activate (&clk_unit, clk_unit.wait); /* activate unit */
|
||||
tmr_poll = clk_unit.wait; /* set timer poll */
|
||||
tmxr_poll = clk_unit.wait; /* set mux poll */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user