mirror of
https://github.com/open-simh/simh.git
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Notes For V3.5-0
The source set has been extensively overhauled. For correct viewing, set Visual C++ or Emacs to have tab stops every 4 characters. 1. New Features in 3.4-1 1.1 All Ethernet devices - Added Windows user-defined adapter names (from Timothe Litt) 1.2 Interdata, SDS, HP, PDP-8, PDP-18b terminal multiplexors - Added support for SET <unit>n DISCONNECT 1.3 VAX - Added latent QDSS support - Revised autoconfigure to handle QDSS 1.4 PDP-11 - Revised autoconfigure to handle more casees 2. Bugs Fixed in 3.4-1 2.1 SCP and libraries - Trim trailing spaces on all input (for example, attach file names) - Fixed sim_sock spurious SIGPIPE error in Unix/Linux - Fixed sim_tape misallocation of TPC map array for 64b simulators 2.2 1401 - Fixed bug, CPU reset was clearing SSB through SSG 2.3 PDP-11 - Fixed bug in VH vector display routine - Fixed XU runt packet processing (found by Tim Chapman) 2.4 Interdata - Fixed bug in SHOW PAS CONN/STATS - Fixed potential integer overflow exception in divide 2.5 SDS - Fixed bug in SHOW MUX CONN/STATS 2.6 HP - Fixed bug in SHOW MUX CONN/STATS 2.7 PDP-8 - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.8 PDP-18b - Fixed bug in SHOW TTIX CONN/STATS - Fixed bug in SET/SHOW TTOXn LOG 2.9 Nova, Eclipse - Fixed potential integer overflow exception in divide
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
ec60bbf329
commit
b7c1eae41f
479
PDP8/pdp8_rf.c
479
PDP8/pdp8_rf.c
@@ -1,6 +1,6 @@
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/* pdp8_rf.c: RF08 fixed head disk simulator
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Copyright (c) 1993-2004, Robert M Supnik
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Copyright (c) 1993-2005, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -19,99 +19,99 @@
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Robert M Supnik shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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rf RF08 fixed head disk
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rf RF08 fixed head disk
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04-Jan-04 RMS Changed sim_fsize calling sequence
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26-Oct-03 RMS Cleaned up buffer copy code
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26-Jul-03 RMS Fixed bug in set size routine
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14-Mar-03 RMS Fixed variable platter interaction with save/restore
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03-Mar-03 RMS Fixed autosizing
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02-Feb-03 RMS Added variable platter and autosizing support
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04-Oct-02 RMS Added DIB, device number support
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28-Nov-01 RMS Added RL8A support
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25-Apr-01 RMS Added device enable/disable support
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19-Mar-01 RMS Added disk monitor bootstrap, fixed IOT decoding
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15-Feb-01 RMS Fixed 3 cycle data break sequence
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14-Apr-99 RMS Changed t_addr to unsigned
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30-Mar-98 RMS Fixed bug in RF bootstrap
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04-Jan-04 RMS Changed sim_fsize calling sequence
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26-Oct-03 RMS Cleaned up buffer copy code
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26-Jul-03 RMS Fixed bug in set size routine
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14-Mar-03 RMS Fixed variable platter interaction with save/restore
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03-Mar-03 RMS Fixed autosizing
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02-Feb-03 RMS Added variable platter and autosizing support
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04-Oct-02 RMS Added DIB, device number support
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28-Nov-01 RMS Added RL8A support
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25-Apr-01 RMS Added device enable/disable support
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19-Mar-01 RMS Added disk monitor bootstrap, fixed IOT decoding
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15-Feb-01 RMS Fixed 3 cycle data break sequence
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14-Apr-99 RMS Changed t_addr to unsigned
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30-Mar-98 RMS Fixed bug in RF bootstrap
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The RF08 is a head-per-track disk. It uses the three cycle data break
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facility. To minimize overhead, the entire RF08 is buffered in memory.
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Two timing parameters are provided:
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rf_time Interword timing, must be non-zero
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rf_burst Burst mode, if 0, DMA occurs cycle by cycle; otherwise,
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DMA occurs in a burst
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rf_time Interword timing, must be non-zero
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rf_burst Burst mode, if 0, DMA occurs cycle by cycle; otherwise,
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DMA occurs in a burst
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*/
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#include "pdp8_defs.h"
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#include <math.h>
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#define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */
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#define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */
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#define UNIT_M_PLAT 03
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#define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)
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#define UNIT_AUTO (1 << UNIT_V_AUTO)
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#define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)
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#define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */
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#define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */
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#define UNIT_M_PLAT 03
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#define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)
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#define UNIT_AUTO (1 << UNIT_V_AUTO)
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#define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)
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/* Constants */
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#define RF_NUMWD 2048 /* words/track */
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#define RF_NUMTR 128 /* tracks/disk */
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#define RF_DKSIZE (RF_NUMTR * RF_NUMWD) /* words/disk */
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#define RF_NUMDK 4 /* disks/controller */
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#define RF_WC 07750 /* word count */
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#define RF_MA 07751 /* mem address */
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#define RF_WMASK (RF_NUMWD - 1) /* word mask */
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#define RF_NUMWD 2048 /* words/track */
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#define RF_NUMTR 128 /* tracks/disk */
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#define RF_DKSIZE (RF_NUMTR * RF_NUMWD) /* words/disk */
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#define RF_NUMDK 4 /* disks/controller */
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#define RF_WC 07750 /* word count */
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#define RF_MA 07751 /* mem address */
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#define RF_WMASK (RF_NUMWD - 1) /* word mask */
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/* Parameters in the unit descriptor */
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#define FUNC u4 /* function */
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#define RF_READ 2 /* read */
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#define RF_WRITE 4 /* write */
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#define FUNC u4 /* function */
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#define RF_READ 2 /* read */
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#define RF_WRITE 4 /* write */
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/* Status register */
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#define RFS_PCA 04000 /* photocell status */
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#define RFS_DRE 02000 /* data req enable */
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#define RFS_WLS 01000 /* write lock status */
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#define RFS_EIE 00400 /* error int enable */
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#define RFS_PIE 00200 /* photocell int enb */
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#define RFS_CIE 00100 /* done int enable */
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#define RFS_MEX 00070 /* memory extension */
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#define RFS_DRL 00004 /* data late error */
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#define RFS_NXD 00002 /* non-existent disk */
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#define RFS_PER 00001 /* parity error */
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#define RFS_ERR (RFS_WLS + RFS_DRL + RFS_NXD + RFS_PER)
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#define RFS_V_MEX 3
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#define RFS_PCA 04000 /* photocell status */
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#define RFS_DRE 02000 /* data req enable */
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#define RFS_WLS 01000 /* write lock status */
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#define RFS_EIE 00400 /* error int enable */
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#define RFS_PIE 00200 /* photocell int enb */
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#define RFS_CIE 00100 /* done int enable */
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#define RFS_MEX 00070 /* memory extension */
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#define RFS_DRL 00004 /* data late error */
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#define RFS_NXD 00002 /* non-existent disk */
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#define RFS_PER 00001 /* parity error */
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#define RFS_ERR (RFS_WLS + RFS_DRL + RFS_NXD + RFS_PER)
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#define RFS_V_MEX 3
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#define GET_MEX(x) (((x) & RFS_MEX) << (12 - RFS_V_MEX))
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) RF_NUMWD)))
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#define UPDATE_PCELL if (GET_POS(rf_time) < 6) rf_sta = rf_sta | RFS_PCA; \
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else rf_sta = rf_sta & ~RFS_PCA
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#define RF_INT_UPDATE if ((rf_done && (rf_sta & RFS_CIE)) || \
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((rf_sta & RFS_ERR) && (rf_sta & RFS_EIE)) || \
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((rf_sta & RFS_PCA) && (rf_sta & RFS_PIE))) \
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int_req = int_req | INT_RF; \
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else int_req = int_req & ~INT_RF
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#define GET_MEX(x) (((x) & RFS_MEX) << (12 - RFS_V_MEX))
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#define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \
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((double) RF_NUMWD)))
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#define UPDATE_PCELL if (GET_POS(rf_time) < 6) rf_sta = rf_sta | RFS_PCA; \
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else rf_sta = rf_sta & ~RFS_PCA
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#define RF_INT_UPDATE if ((rf_done && (rf_sta & RFS_CIE)) || \
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((rf_sta & RFS_ERR) && (rf_sta & RFS_EIE)) || \
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((rf_sta & RFS_PCA) && (rf_sta & RFS_PIE))) \
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int_req = int_req | INT_RF; \
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else int_req = int_req & ~INT_RF
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extern uint16 M[];
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extern int32 int_req, stop_inst;
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extern UNIT cpu_unit;
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int32 rf_sta = 0; /* status register */
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int32 rf_da = 0; /* disk address */
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int32 rf_done = 0; /* done flag */
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int32 rf_wlk = 0; /* write lock */
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int32 rf_time = 10; /* inter-word time */
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int32 rf_burst = 1; /* burst mode flag */
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int32 rf_stopioe = 1; /* stop on error */
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int32 rf_sta = 0; /* status register */
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int32 rf_da = 0; /* disk address */
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int32 rf_done = 0; /* done flag */
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int32 rf_wlk = 0; /* write lock */
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int32 rf_time = 10; /* inter-word time */
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int32 rf_burst = 1; /* burst mode flag */
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int32 rf_stopioe = 1; /* stop on error */
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DEVICE rf_dev;
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int32 rf60 (int32 IR, int32 AC);
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@@ -127,52 +127,56 @@ t_stat rf_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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/* RF08 data structures
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rf_dev RF device descriptor
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rf_unit RF unit descriptor
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pcell_unit photocell timing unit (orphan)
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rf_reg RF register list
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rf_dev RF device descriptor
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rf_unit RF unit descriptor
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pcell_unit photocell timing unit (orphan)
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rf_reg RF register list
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*/
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DIB rf_dib = { DEV_RF, 5, { &rf60, &rf61, &rf62, NULL, &rf64 } };
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UNIT rf_unit =
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{ UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+
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UNIT_BUFABLE+UNIT_MUSTBUF, RF_DKSIZE) };
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UNIT rf_unit = {
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UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+
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UNIT_BUFABLE+UNIT_MUSTBUF, RF_DKSIZE)
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};
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UNIT pcell_unit = { UDATA (&pcell_svc, 0, 0) };
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REG rf_reg[] = {
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{ ORDATA (STA, rf_sta, 12) },
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{ ORDATA (DA, rf_da, 20) },
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{ ORDATA (WC, M[RF_WC], 12) },
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{ ORDATA (MA, M[RF_MA], 12) },
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{ FLDATA (DONE, rf_done, 0) },
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{ FLDATA (INT, int_req, INT_V_RF) },
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{ ORDATA (WLK, rf_wlk, 32) },
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{ DRDATA (TIME, rf_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (BURST, rf_burst, 0) },
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{ FLDATA (STOP_IOE, rf_stopioe, 0) },
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{ DRDATA (CAPAC, rf_unit.capac, 21), REG_HRO },
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{ ORDATA (DEVNUM, rf_dib.dev, 6), REG_HRO },
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{ NULL } };
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{ ORDATA (STA, rf_sta, 12) },
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{ ORDATA (DA, rf_da, 20) },
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{ ORDATA (WC, M[RF_WC], 12) },
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{ ORDATA (MA, M[RF_MA], 12) },
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{ FLDATA (DONE, rf_done, 0) },
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{ FLDATA (INT, int_req, INT_V_RF) },
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{ ORDATA (WLK, rf_wlk, 32) },
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{ DRDATA (TIME, rf_time, 24), REG_NZ + PV_LEFT },
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{ FLDATA (BURST, rf_burst, 0) },
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{ FLDATA (STOP_IOE, rf_stopioe, 0) },
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{ DRDATA (CAPAC, rf_unit.capac, 21), REG_HRO },
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{ ORDATA (DEVNUM, rf_dib.dev, 6), REG_HRO },
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{ NULL }
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};
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MTAB rf_mod[] = {
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{ UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rf_set_size },
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{ UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rf_set_size },
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{ UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rf_set_size },
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{ UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rf_set_size },
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{ UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, NULL },
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{ 0 } };
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{ UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rf_set_size },
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{ UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rf_set_size },
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{ UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rf_set_size },
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{ UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rf_set_size },
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{ UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },
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{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
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&set_dev, &show_dev, NULL },
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{ 0 }
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};
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DEVICE rf_dev = {
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"RF", &rf_unit, rf_reg, rf_mod,
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1, 8, 20, 1, 8, 12,
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NULL, NULL, &rf_reset,
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&rf_boot, &rf_attach, NULL,
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&rf_dib, DEV_DISABLE | DEV_DIS };
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"RF", &rf_unit, rf_reg, rf_mod,
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1, 8, 20, 1, 8, 12,
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NULL, NULL, &rf_reset,
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&rf_boot, &rf_attach, NULL,
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&rf_dib, DEV_DISABLE | DEV_DIS
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};
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/* IOT routines */
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int32 rf60 (int32 IR, int32 AC)
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@@ -180,19 +184,21 @@ int32 rf60 (int32 IR, int32 AC)
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int32 t;
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DCMA */
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rf_da = rf_da & ~07777; /* clear DAR<8:19> */
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rf_done = 0; /* clear done */
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rf_sta = rf_sta & ~RFS_ERR; /* clear errors */
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RF_INT_UPDATE; } /* update int req */
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if (pulse & 6) { /* DMAR, DMAW */
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rf_da = rf_da | AC; /* DAR<8:19> |= AC */
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rf_unit.FUNC = pulse & ~1; /* save function */
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t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new loc */
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if (t < 0) t = t + RF_NUMWD; /* wrap around? */
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sim_activate (&rf_unit, t * rf_time); /* schedule op */
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AC = 0; } /* clear AC */
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UPDATE_PCELL; /* update photocell */
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if (pulse & 1) { /* DCMA */
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rf_da = rf_da & ~07777; /* clear DAR<8:19> */
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rf_done = 0; /* clear done */
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rf_sta = rf_sta & ~RFS_ERR; /* clear errors */
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RF_INT_UPDATE; /* update int req */
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}
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if (pulse & 6) { /* DMAR, DMAW */
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rf_da = rf_da | AC; /* DAR<8:19> |= AC */
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rf_unit.FUNC = pulse & ~1; /* save function */
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t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new loc */
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if (t < 0) t = t + RF_NUMWD; /* wrap around? */
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sim_activate (&rf_unit, t * rf_time); /* schedule op */
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AC = 0; /* clear AC */
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}
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return AC;
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}
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@@ -200,41 +206,47 @@ int32 rf61 (int32 IR, int32 AC)
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{
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int32 pulse = IR & 07;
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCIM */
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rf_sta = rf_sta & 07007; /* clear STA<3:8> */
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int_req = int_req & ~INT_RF; /* clear int req */
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sim_cancel (&pcell_unit); /* cancel photocell */
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return AC;
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case 2: /* DSAC */
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return ((rf_da & RF_WMASK) == GET_POS (rf_time))? IOT_SKP: 0;
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case 5: /* DIML */
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rf_sta = (rf_sta & 07007) | (AC & 0770); /* STA<3:8> <- AC */
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if (rf_sta & RFS_PIE) /* photocell int? */
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sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
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rf_time);
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else sim_cancel (&pcell_unit);
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RF_INT_UPDATE; /* update int req */
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return 0; /* clear AC */
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case 6: /* DIMA */
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return rf_sta; } /* AC <- STA<0:11> */
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UPDATE_PCELL; /* update photocell */
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switch (pulse) { /* decode IR<9:11> */
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case 1: /* DCIM */
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rf_sta = rf_sta & 07007; /* clear STA<3:8> */
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int_req = int_req & ~INT_RF; /* clear int req */
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sim_cancel (&pcell_unit); /* cancel photocell */
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return AC;
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case 2: /* DSAC */
|
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return ((rf_da & RF_WMASK) == GET_POS (rf_time))? IOT_SKP: 0;
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case 5: /* DIML */
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rf_sta = (rf_sta & 07007) | (AC & 0770); /* STA<3:8> <- AC */
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if (rf_sta & RFS_PIE) /* photocell int? */
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sim_activate (&pcell_unit, (RF_NUMWD - GET_POS (rf_time)) *
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rf_time);
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else sim_cancel (&pcell_unit);
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RF_INT_UPDATE; /* update int req */
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return 0; /* clear AC */
|
||||
|
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case 6: /* DIMA */
|
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return rf_sta; /* AC <- STA<0:11> */
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}
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return AC;
|
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}
|
||||
|
||||
/* IOT's, continued */
|
||||
|
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int32 rf62 (int32 IR, int32 AC)
|
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{
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int32 pulse = IR & 07;
|
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|
||||
UPDATE_PCELL; /* update photocell */
|
||||
if (pulse & 1) { /* DFSE */
|
||||
if (rf_sta & RFS_ERR) AC = AC | IOT_SKP; }
|
||||
if (pulse & 2) { /* DFSC */
|
||||
if (pulse & 4) AC = AC & ~07777; /* for DMAC */
|
||||
else if (rf_done) AC = AC | IOT_SKP; }
|
||||
if (pulse & 4) AC = AC | (rf_da & 07777); /* DMAC */
|
||||
UPDATE_PCELL; /* update photocell */
|
||||
if (pulse & 1) { /* DFSE */
|
||||
if (rf_sta & RFS_ERR) AC = AC | IOT_SKP;
|
||||
}
|
||||
if (pulse & 2) { /* DFSC */
|
||||
if (pulse & 4) AC = AC & ~07777; /* for DMAC */
|
||||
else if (rf_done) AC = AC | IOT_SKP;
|
||||
}
|
||||
if (pulse & 4) AC = AC | (rf_da & 07777); /* DMAC */
|
||||
return AC;
|
||||
}
|
||||
|
||||
@@ -242,31 +254,37 @@ int32 rf64 (int32 IR, int32 AC)
|
||||
{
|
||||
int32 pulse = IR & 07;
|
||||
|
||||
UPDATE_PCELL; /* update photocell */
|
||||
switch (pulse) { /* decode IR<9:11> */
|
||||
case 1: /* DCXA */
|
||||
rf_da = rf_da & 07777; /* clear DAR<0:7> */
|
||||
break;
|
||||
case 3: /* DXAL */
|
||||
rf_da = rf_da & 07777; /* clear DAR<0:7> */
|
||||
case 2: /* DXAL w/o clear */
|
||||
rf_da = rf_da | ((AC & 0377) << 12); /* DAR<0:7> |= AC */
|
||||
AC = AC & ~07777; /* clear AC */
|
||||
break;
|
||||
case 5: /* DXAC */
|
||||
AC = AC & ~07777; /* clear AC */
|
||||
case 4: /* DXAC w/o clear */
|
||||
AC = AC | ((rf_da >> 12) & 0377); /* AC |= DAR<0:7> */
|
||||
break;
|
||||
default:
|
||||
AC = (stop_inst << IOT_V_REASON) + AC;
|
||||
break; } /* end switch */
|
||||
UPDATE_PCELL; /* update photocell */
|
||||
switch (pulse) { /* decode IR<9:11> */
|
||||
|
||||
case 1: /* DCXA */
|
||||
rf_da = rf_da & 07777; /* clear DAR<0:7> */
|
||||
break;
|
||||
|
||||
case 3: /* DXAL */
|
||||
rf_da = rf_da & 07777; /* clear DAR<0:7> */
|
||||
case 2: /* DXAL w/o clear */
|
||||
rf_da = rf_da | ((AC & 0377) << 12); /* DAR<0:7> |= AC */
|
||||
AC = 0; /* clear AC */
|
||||
break;
|
||||
|
||||
case 5: /* DXAC */
|
||||
AC = 0; /* clear AC */
|
||||
case 4: /* DXAC w/o clear */
|
||||
AC = AC | ((rf_da >> 12) & 0377); /* AC |= DAR<0:7> */
|
||||
break;
|
||||
|
||||
default:
|
||||
AC = (stop_inst << IOT_V_REASON) + AC;
|
||||
break;
|
||||
} /* end switch */
|
||||
|
||||
if ((uint32) rf_da >= rf_unit.capac) rf_sta = rf_sta | RFS_NXD;
|
||||
else rf_sta = rf_sta & ~RFS_NXD;
|
||||
RF_INT_UPDATE;
|
||||
return AC;
|
||||
}
|
||||
|
||||
|
||||
/* Unit service
|
||||
|
||||
Note that for reads and writes, memory addresses wrap around in the
|
||||
@@ -278,37 +296,45 @@ t_stat rf_svc (UNIT *uptr)
|
||||
int32 pa, t, mex;
|
||||
int16 *fbuf = uptr->filebuf;
|
||||
|
||||
UPDATE_PCELL; /* update photocell */
|
||||
if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
|
||||
rf_sta = rf_sta | RFS_NXD;
|
||||
rf_done = 1;
|
||||
RF_INT_UPDATE; /* update int req */
|
||||
return IORETURN (rf_stopioe, SCPE_UNATT); }
|
||||
UPDATE_PCELL; /* update photocell */
|
||||
if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */
|
||||
rf_sta = rf_sta | RFS_NXD;
|
||||
rf_done = 1;
|
||||
RF_INT_UPDATE; /* update int req */
|
||||
return IORETURN (rf_stopioe, SCPE_UNATT);
|
||||
}
|
||||
|
||||
mex = GET_MEX (rf_sta);
|
||||
do { if ((uint32) rf_da >= rf_unit.capac) { /* disk overflow? */
|
||||
rf_sta = rf_sta | RFS_NXD;
|
||||
break; }
|
||||
M[RF_WC] = (M[RF_WC] + 1) & 07777; /* incr word count */
|
||||
M[RF_MA] = (M[RF_MA] + 1) & 07777; /* incr mem addr */
|
||||
pa = mex | M[RF_MA]; /* add extension */
|
||||
if (uptr->FUNC == RF_READ) { /* read? */
|
||||
if (MEM_ADDR_OK (pa)) /* if !nxm */
|
||||
M[pa] = fbuf[rf_da]; } /* read word */
|
||||
else { /* write */
|
||||
t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
|
||||
if ((rf_wlk >> t) & 1) /* write locked? */
|
||||
rf_sta = rf_sta | RFS_WLS;
|
||||
else { /* not locked */
|
||||
fbuf[rf_da] = M[pa]; /* write word */
|
||||
if (((uint32) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1; } }
|
||||
rf_da = (rf_da + 1) & 03777777; } /* incr disk addr */
|
||||
while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
|
||||
do {
|
||||
if ((uint32) rf_da >= rf_unit.capac) { /* disk overflow? */
|
||||
rf_sta = rf_sta | RFS_NXD;
|
||||
break;
|
||||
}
|
||||
M[RF_WC] = (M[RF_WC] + 1) & 07777; /* incr word count */
|
||||
M[RF_MA] = (M[RF_MA] + 1) & 07777; /* incr mem addr */
|
||||
pa = mex | M[RF_MA]; /* add extension */
|
||||
if (uptr->FUNC == RF_READ) { /* read? */
|
||||
if (MEM_ADDR_OK (pa)) /* if !nxm */
|
||||
M[pa] = fbuf[rf_da]; /* read word */
|
||||
}
|
||||
else { /* write */
|
||||
t = ((rf_da >> 15) & 030) | ((rf_da >> 14) & 07);
|
||||
if ((rf_wlk >> t) & 1) /* write locked? */
|
||||
rf_sta = rf_sta | RFS_WLS;
|
||||
else { /* not locked */
|
||||
fbuf[rf_da] = M[pa]; /* write word */
|
||||
if (((uint32) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1;
|
||||
}
|
||||
}
|
||||
rf_da = (rf_da + 1) & 03777777; /* incr disk addr */
|
||||
} while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */
|
||||
|
||||
if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */
|
||||
sim_activate (&rf_unit, rf_time); /* sched next */
|
||||
else { rf_done = 1; /* done */
|
||||
RF_INT_UPDATE; } /* update int req */
|
||||
if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */
|
||||
sim_activate (&rf_unit, rf_time); /* sched next */
|
||||
else {
|
||||
rf_done = 1; /* done */
|
||||
RF_INT_UPDATE; /* update int req */
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -316,20 +342,21 @@ return SCPE_OK;
|
||||
|
||||
t_stat pcell_svc (UNIT *uptr)
|
||||
{
|
||||
rf_sta = rf_sta | RFS_PCA; /* set photocell */
|
||||
if (rf_sta & RFS_PIE) { /* int enable? */
|
||||
sim_activate (&pcell_unit, RF_NUMWD * rf_time);
|
||||
int_req = int_req | INT_RF; }
|
||||
rf_sta = rf_sta | RFS_PCA; /* set photocell */
|
||||
if (rf_sta & RFS_PIE) { /* int enable? */
|
||||
sim_activate (&pcell_unit, RF_NUMWD * rf_time);
|
||||
int_req = int_req | INT_RF;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
|
||||
/* Reset routine */
|
||||
|
||||
t_stat rf_reset (DEVICE *dptr)
|
||||
{
|
||||
rf_sta = rf_da = 0;
|
||||
rf_done = 1;
|
||||
int_req = int_req & ~INT_RF; /* clear interrupt */
|
||||
int_req = int_req & ~INT_RF; /* clear interrupt */
|
||||
sim_cancel (&rf_unit);
|
||||
sim_cancel (&pcell_unit);
|
||||
return SCPE_OK;
|
||||
@@ -337,42 +364,45 @@ return SCPE_OK;
|
||||
|
||||
/* Bootstrap routine */
|
||||
|
||||
#define OS8_START 07750
|
||||
#define OS8_LEN (sizeof (os8_rom) / sizeof (int16))
|
||||
#define DM4_START 00200
|
||||
#define DM4_LEN (sizeof (dm4_rom) / sizeof (int16))
|
||||
#define OS8_START 07750
|
||||
#define OS8_LEN (sizeof (os8_rom) / sizeof (int16))
|
||||
#define DM4_START 00200
|
||||
#define DM4_LEN (sizeof (dm4_rom) / sizeof (int16))
|
||||
|
||||
static const uint16 os8_rom[] = {
|
||||
07600, /* 7750, CLA CLL ; also word count */
|
||||
06603, /* 7751, DMAR ; also address */
|
||||
06622, /* 7752, DFSC ; done? */
|
||||
05352, /* 7753, JMP .-1 ; no */
|
||||
05752 /* 7754, JMP @.-2 ; enter boot */
|
||||
};
|
||||
07600, /* 7750, CLA CLL ; also word count */
|
||||
06603, /* 7751, DMAR ; also address */
|
||||
06622, /* 7752, DFSC ; done? */
|
||||
05352, /* 7753, JMP .-1 ; no */
|
||||
05752 /* 7754, JMP @.-2 ; enter boot */
|
||||
};
|
||||
|
||||
static const uint16 dm4_rom[] = {
|
||||
00200, 07600, /* 0200, CLA CLL */
|
||||
00201, 06603, /* 0201, DMAR ; read */
|
||||
00202, 06622, /* 0202, DFSC ; done? */
|
||||
00203, 05202, /* 0203, JMP .-1 ; no */
|
||||
00204, 05600, /* 0204, JMP @.-4 ; enter boot */
|
||||
07750, 07576, /* 7750, 7576 ; word count */
|
||||
07751, 07576 /* 7751, 7576 ; address */
|
||||
};
|
||||
00200, 07600, /* 0200, CLA CLL */
|
||||
00201, 06603, /* 0201, DMAR ; read */
|
||||
00202, 06622, /* 0202, DFSC ; done? */
|
||||
00203, 05202, /* 0203, JMP .-1 ; no */
|
||||
00204, 05600, /* 0204, JMP @.-4 ; enter boot */
|
||||
07750, 07576, /* 7750, 7576 ; word count */
|
||||
07751, 07576 /* 7751, 7576 ; address */
|
||||
};
|
||||
|
||||
t_stat rf_boot (int32 unitno, DEVICE *dptr)
|
||||
{
|
||||
int32 i;
|
||||
extern int32 sim_switches, saved_PC;
|
||||
|
||||
if (rf_dib.dev != DEV_RF) return STOP_NOTSTD; /* only std devno */
|
||||
if (rf_dib.dev != DEV_RF) return STOP_NOTSTD; /* only std devno */
|
||||
if (sim_switches & SWMASK ('D')) {
|
||||
for (i = 0; i < DM4_LEN; i = i + 2)
|
||||
M[dm4_rom[i]] = dm4_rom[i + 1];
|
||||
saved_PC = DM4_START; }
|
||||
else { for (i = 0; i < OS8_LEN; i++)
|
||||
M[OS8_START + i] = os8_rom[i];
|
||||
saved_PC = OS8_START; }
|
||||
for (i = 0; i < DM4_LEN; i = i + 2)
|
||||
M[dm4_rom[i]] = dm4_rom[i + 1];
|
||||
saved_PC = DM4_START;
|
||||
}
|
||||
else {
|
||||
for (i = 0; i < OS8_LEN; i++)
|
||||
M[OS8_START + i] = os8_rom[i];
|
||||
saved_PC = OS8_START;
|
||||
}
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
@@ -387,10 +417,11 @@ t_stat r;
|
||||
r = attach_unit (uptr, cptr);
|
||||
if (r != SCPE_OK) return r;
|
||||
if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize (uptr->fileref))) {
|
||||
p = (sz + ds_bytes - 1) / ds_bytes;
|
||||
if (p >= RF_NUMDK) p = RF_NUMDK - 1;
|
||||
uptr->flags = (uptr->flags & ~UNIT_PLAT) |
|
||||
(p << UNIT_V_PLAT); }
|
||||
p = (sz + ds_bytes - 1) / ds_bytes;
|
||||
if (p >= RF_NUMDK) p = RF_NUMDK - 1;
|
||||
uptr->flags = (uptr->flags & ~UNIT_PLAT) |
|
||||
(p << UNIT_V_PLAT);
|
||||
}
|
||||
uptr->capac = UNIT_GETP (uptr->flags) * RF_DKSIZE;
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user