diff --git a/3B2/3b2_ctc.c b/3B2/3b2_ctc.c
index 9386e5bb..819764b7 100644
--- a/3B2/3b2_ctc.c
+++ b/3B2/3b2_ctc.c
@@ -257,7 +257,7 @@ static void ctc_cmd(uint8 cid,
uint8 dev;
uint8 sec_buf[512];
int32 secrw = 0;
- int32 b;
+ int32 b, j;
struct vtoc vtoc = {0};
struct pdinfo pdinfo = {0};
@@ -481,7 +481,7 @@ static void ctc_cmd(uint8 cid,
for (b = 0; b < rqe->byte_count / 512; b++) {
ctc_state[dev].time += 10;
- for (int j = 0; j < 512; j++) {
+ for (j = 0; j < 512; j++) {
/* Fill the buffer */
sec_buf[j] = pread_b(rqe->address + (b * 512) + j);
}
@@ -522,7 +522,7 @@ static void ctc_cmd(uint8 cid,
"[ctc_cmd] ... CTC_READ: 512 bytes from block %d (0x%x)\n",
lba, lba);
sim_disk_rdsect(&ctc_unit, lba, sec_buf, &secrw, 1);
- for (int j = 0; j < 512; j++) {
+ for (j = 0; j < 512; j++) {
/* Drain the buffer */
pwrite_b(rqe->address + (b * 512) + j, sec_buf[j]);
}
@@ -605,8 +605,7 @@ void ctc_full(uint8 cid)
t_stat ctc_reset(DEVICE *dptr)
{
- uint32 i;
- uint8 cid, end_slot;
+ uint8 cid;
sim_debug(TRACE_DBG, &ctc_dev,
"[ctc_reset] Resetting CTC device\n");
diff --git a/3B2/3b2_io.c b/3B2/3b2_io.c
index 61f58d70..233ea5e0 100644
--- a/3B2/3b2_io.c
+++ b/3B2/3b2_io.c
@@ -119,7 +119,8 @@ void cio_sysgen(uint8 cid)
void cio_cexpress(uint8 cid, uint16 esize, cio_entry *cqe, uint8 *app_data)
{
- uint32 cqp, i;
+ int32 i;
+ uint32 cqp;
cqp = cio[cid].cqp;
@@ -145,7 +146,8 @@ void cio_cexpress(uint8 cid, uint16 esize, cio_entry *cqe, uint8 *app_data)
void cio_cqueue(uint8 cid, uint8 cmd_stat, uint16 esize,
cio_entry *cqe, uint8 *app_data)
{
- uint32 cqp, top, i;
+ int32 i;
+ uint32 cqp, top;
uint16 lp, ulp;
/* Apply the CMD/STAT bit */
@@ -195,7 +197,8 @@ void cio_cqueue(uint8 cid, uint8 cmd_stat, uint16 esize,
*/
void cio_rexpress(uint8 cid, uint16 esize, cio_entry *rqe, uint8 *app_data)
{
- uint32 rqp, i;
+ int32 i;
+ uint32 rqp;
rqp = cio[cid].rqp;
@@ -221,7 +224,8 @@ void cio_rexpress(uint8 cid, uint16 esize, cio_entry *rqe, uint8 *app_data)
t_stat cio_rqueue(uint8 cid, uint8 qnum, uint16 esize,
cio_entry *rqe, uint8 *app_data)
{
- uint32 rqp, top, i;
+ int32 i;
+ uint32 rqp, top;
uint16 lp, ulp;
/* Get the physical address of the request queue in main memory */
@@ -306,7 +310,7 @@ uint16 cio_c_ulp(uint8 cid, uint16 esize)
* Returns true if there is room in the completion queue
* for a new entry.
*/
-t_bool cio_cqueue_avail(uint cid, uint16 esize)
+t_bool cio_cqueue_avail(uint8 cid, uint16 esize)
{
uint32 lp, ulp;
@@ -611,8 +615,6 @@ void io_write(uint32 pa, uint32 val, size_t size)
void dump_entry(uint32 dbits, DEVICE *dev, CONST char *type,
uint16 esize, cio_entry *entry, uint8 *app_data)
{
- uint32 i;
-
sim_debug(dbits, dev,
"*** %s ENTRY: byte_count=%04x, subdevice=%02x, opcode=%d, address=%08x\n",
type, entry->byte_count, entry->subdevice,
diff --git a/3B2/3b2_io.h b/3B2/3b2_io.h
index 1fbc65ec..8818f755 100644
--- a/3B2/3b2_io.h
+++ b/3B2/3b2_io.h
@@ -221,12 +221,10 @@ t_stat cio_svc(UNIT *uptr);
void cio_clear(uint8 cid);
void cio_cexpress(uint8 cid, uint16 esize, cio_entry *cqe, uint8 *app_data);
-void cio_cqueue(uint8 cid, uint8 cmd_stat, uint16 esize,
- cio_entry *cqe, uint8 *app_data);
+void cio_cqueue(uint8 cid, uint8 cmd_stat, uint16 esize, cio_entry *cqe, uint8 *app_data);
void cio_rexpress(uint8 cid, uint16 esize, cio_entry *rqe, uint8 *app_data);
-t_stat cio_rqueue(uint8 cid, uint8 qnum, uint16 esize,
- cio_entry *rqe, uint8 *app_data);
-t_bool cio_cqueue_avail(uint cid, uint16 esize);
+t_stat cio_rqueue(uint8 cid, uint8 qnum, uint16 esize, cio_entry *rqe, uint8 *app_data);
+t_bool cio_cqueue_avail(uint8 cid, uint16 esize);
uint16 cio_r_lp(uint8 cid, uint8 qnum, uint16 esize);
uint16 cio_r_ulp(uint8 cid, uint8 qnum, uint16 esize);
uint16 cio_c_lp(uint8 cid, uint16 esize);
diff --git a/3B2/3b2_iu.c b/3B2/3b2_iu.c
index 75e5dd5b..b754f017 100644
--- a/3B2/3b2_iu.c
+++ b/3B2/3b2_iu.c
@@ -608,7 +608,7 @@ uint32 iu_read(uint32 pa, size_t size)
case START_CTR:
data = 0;
iu_state.istat &= ~ISTS_CRI;
- sim_activate_abs(&iu_timer_unit, iu_timer_state.c_set * IU_TIMER_RATE);
+ sim_activate_abs(&iu_timer_unit, (int32)(iu_timer_state.c_set * IU_TIMER_RATE));
break;
case STOP_CTR:
data = 0;
diff --git a/3B2/3b2_ports.c b/3B2/3b2_ports.c
index 281e5df3..4d37d2a7 100644
--- a/3B2/3b2_ports.c
+++ b/3B2/3b2_ports.c
@@ -188,7 +188,7 @@ static void cio_irq(uint8 cid, uint8 dev, int32 delay)
*/
t_stat ports_setnl(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
{
- int32 newln, newcards, i, t;
+ int32 newln, i, t;
t_stat r = SCPE_OK;
if (cptr == NULL) {
@@ -247,8 +247,7 @@ t_stat ports_setnl(UNIT *uptr, int32 val, CONST char *cptr, void *desc)
static void ports_cmd(uint8 cid, cio_entry *rentry, uint8 *rapp_data)
{
cio_entry centry = {0};
- uint32 i, ln;
- char c;
+ uint32 ln;
PORTS_OPTIONS opts;
char line_config[16];
uint8 app_data[4] = {0};
@@ -524,7 +523,7 @@ void ports_express(uint8 cid)
void ports_full(uint8 cid)
{
- uint32 i, ln;
+ uint32 i;
cio_entry rqe;
uint8 app_data[4] = {0};
@@ -537,8 +536,8 @@ void ports_full(uint8 cid)
t_stat ports_reset(DEVICE *dptr)
{
- uint32 i;
- uint8 cid, line, cards, ln, end_slot;
+ int32 i;
+ uint8 cid, line, ln, end_slot;
TMLN *lp;
sim_debug(TRACE_DBG, &ports_dev,
diff --git a/Visual Studio Projects/3B2.vcproj b/Visual Studio Projects/3B2.vcproj
index 6cdd7525..ee4d0071 100644
--- a/Visual Studio Projects/3B2.vcproj
+++ b/Visual Studio Projects/3B2.vcproj
@@ -35,6 +35,9 @@
+
@@ -116,6 +119,9 @@
+
@@ -192,6 +198,10 @@
RelativePath="..\3B2\3b2_cpu.c"
>
+
+
@@ -216,6 +226,10 @@
RelativePath="..\3B2\3b2_mmu.c"
>
+
+
@@ -277,6 +291,10 @@
RelativePath="..\3B2\3b2_cpu.h"
>
+
+
@@ -305,6 +323,10 @@
RelativePath="..\3B2\3b2_mmu.h"
>
+
+