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Notes For V3.6-0
The save/restore format has been updated to improve its reliability. As a result, save files prior to release 3.0 are no longer supported. The text documentation files are obsolete and are no longer included with the distribution. Up-to-date PDF documentation files are available on the SimH web site. 1. New Features 1.1 3.6-0 1.1.1 Most magnetic tapes - Added support for limiting tape capacity to a particular size in MB 1.1.2 IBM 7090/7094 - First release 1.1.3 VAX-11/780 - Added FLOAD command, loads system file from console floppy disk 1.1.4 VAX, VAX-11/780, and PDP-11 - Added card reader support (from John Dundas) 1.1.5 PDP-11 - Added instruction history 2. Bugs Fixed Please see the revision history on http://simh.trailing-edge.com or in the source module sim_rev.h.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
a12e4a1c39
commit
dc871fa631
@@ -1,6 +1,6 @@
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/* id16_cpu.c: Interdata 16b CPU simulator
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Copyright (c) 2000-2005, Robert M. Supnik
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Copyright (c) 2000-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,7 @@
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cpu Interdata 16b CPU
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06-Feb-06 RMS Fixed bug in DH (found by Mark Hittinger)
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22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
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25-Aug-05 RMS Fixed DH integer overflow cases
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16-Aug-05 RMS Fixed C++ declaration and cast problems
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@@ -169,6 +170,7 @@ typedef struct {
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uint16 opnd;
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} InstHistory;
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#define PSW_GETMAP(x) (((x) >> PSW_V_MAP) & PSW_M_MAP)
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#define SEXT16(x) (((x) & SIGN16)? ((int32) ((x) | 0xFFFF8000)): \
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((int32) ((x) & 0x7FFF)))
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#define CC_GL_16(x) if ((x) & SIGN16) cc = CC_L; \
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@@ -1058,7 +1060,7 @@ while (reason == 0) { /* loop until halted */
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case 0x4D: /* DH - RXH */
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r1p1 = (r1 + 1) & 0xF; /* R1 + 1 */
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if ((opnd == 0) ||
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((R[r1] == 0x8000) && (R[r1p1] == 0) && (opnd = 0xFFFF))) {
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((R[r1] == 0x8000) && (R[r1p1] == 0) && (opnd == 0xFFFF))) {
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if (PSW & PSW_AFI) /* div fault enabled? */
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cc = swap_psw (AFIPSW, cc); /* swap PSW */
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break;
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@@ -1,6 +1,6 @@
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/* id32_cpu.c: Interdata 32b CPU simulator
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Copyright (c) 2000-2005, Robert M. Supnik
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Copyright (c) 2000-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,8 @@
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cpu Interdata 32b CPU
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09-Mar-06 RMS Added 8 register bank support for 8/32
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06-Feb-06 RMS Fixed bug in DH (found by Mark Hittinger)
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22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
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16-Aug-05 RMS Fixed C++ declaration and cast problems
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10-Mar-05 RMS Fixed bug in initial memory allocation
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@@ -156,7 +158,7 @@
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#define PCQ_MASK (PCQ_SIZE - 1)
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#define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = oPC
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#define VAMASK VAMASK32
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#define NRSETS 2 /* 2 gen reg sets */
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#define NRSETS 8 /* up to 8 reg sets */
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#define PSW_MASK PSW_x32
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#define ABORT(val) longjmp (save_env, (val))
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#define MPRO (-1)
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@@ -164,9 +166,11 @@
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#define UNIT_V_MSIZE (UNIT_V_UF + 0) /* dummy mask */
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#define UNIT_V_DPFP (UNIT_V_UF + 1)
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#define UNIT_V_832 (UNIT_V_UF + 2)
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#define UNIT_V_8RS (UNIT_V_UF + 3)
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#define UNIT_MSIZE (1 << UNIT_V_MSIZE)
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#define UNIT_DPFP (1 << UNIT_V_DPFP)
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#define UNIT_832 (1 << UNIT_V_832)
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#define UNIT_8RS (1 << UNIT_V_8RS)
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#define UNIT_TYPE (UNIT_DPFP | UNIT_832)
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#define HIST_PC 0x40000000
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@@ -183,6 +187,7 @@ typedef struct {
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uint32 opnd;
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} InstHistory;
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#define PSW_GETREG(x) (((x) >> PSW_V_REG) & psw_reg_mask)
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#define SEXT32(x) (((x) & SIGN32)? ((int32) ((x) | ~0x7FFFFFFF)): \
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((int32) ((x) & 0x7FFFFFFF)))
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#define SEXT16(x) (((x) & SIGN16)? ((int32) ((x) | ~0x7FFF)): \
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@@ -235,6 +240,7 @@ uint32 fp_in_hwre = 0; /* ucode vs hwre fp */
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uint32 pawidth = PAWIDTH32; /* addr mask */
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uint32 hst_p = 0; /* history pointer */
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uint32 hst_lnt = 0; /* history length */
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uint32 psw_reg_mask = 1; /* PSW reg mask */
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InstHistory *hst = NULL; /* instruction history */
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jmp_buf save_env; /* abort handler */
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struct BlockIO blk_io; /* block I/O status */
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@@ -565,10 +571,14 @@ MTAB cpu_mod[] = {
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{ UNIT_MSIZE, 262144, NULL, "256K", &cpu_set_size },
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{ UNIT_MSIZE, 524288, NULL, "512K", &cpu_set_size },
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{ UNIT_MSIZE, 1048756, NULL, "1M", &cpu_set_size },
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{ UNIT_TYPE, 0, "7/32, single precision fp", "732", NULL },
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{ UNIT_8RS|UNIT_TYPE, 0, NULL, "732", NULL },
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{ UNIT_DPFP, UNIT_DPFP, NULL, "DPFP", NULL },
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{ UNIT_TYPE, 0, "7/32, single precision fp", "732", NULL },
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{ UNIT_TYPE, UNIT_DPFP, "7/32, double precision fp", NULL, NULL },
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{ UNIT_TYPE, UNIT_DPFP | UNIT_832, "8/32", "832", NULL },
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{ UNIT_8RS|UNIT_TYPE, UNIT_8RS|UNIT_DPFP|UNIT_832, NULL, "832", NULL },
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{ UNIT_8RS, 0, NULL, "2RS", NULL },
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{ UNIT_8RS|UNIT_TYPE, UNIT_8RS|UNIT_DPFP|UNIT_832, "832, 8 register sets", NULL, NULL },
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{ UNIT_8RS|UNIT_TYPE, UNIT_DPFP|UNIT_832, "832, 2 register sets", NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, NULL, "CONSINT",
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&cpu_set_consint, NULL, NULL },
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{ MTAB_XTD|MTAB_VDV|MTAB_NMO|MTAB_SHP, 0, "HISTORY", "HISTORY",
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@@ -608,6 +618,8 @@ else {
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fp_in_hwre = 0; /* fp in ucode */
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dec_flgs = OP_DPF; /* sp only */
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}
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if (cpu_unit.flags & UNIT_8RS) psw_reg_mask = 7; /* 8 register sets */
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else psw_reg_mask = 1; /* 2 register sets */
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int_eval (); /* eval interrupts */
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cc = newPSW (PSW & PSW_MASK); /* split PSW, eval wait */
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sim_rtcn_init (lfc_unit.wait, TMR_LFC); /* init clock */
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@@ -1223,7 +1235,7 @@ while (reason == 0) { /* loop until halted */
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case 0x4D: /* DH - RXH */
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opnd = opnd & DMASK16; /* force HW opnd */
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if ((opnd == 0) || /* div by zero? */
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((R[r1] == 0x80000000) && (opnd = 0xFFFF))) {
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((R[r1] == 0x80000000) && (opnd == 0xFFFF))) {
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if (PSW & PSW_AFI) /* div fault enabled? */
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cc = exception (AFIPSW, cc, 0); /* exception */
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break;
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@@ -1,6 +1,6 @@
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/* id_defs.h: Interdata 16b/32b simulator definitions
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Copyright (c) 2000-2005, Robert M. Supnik
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Copyright (c) 2000-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -26,6 +26,7 @@
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The author gratefully acknowledges the help of Carl Friend and Al Kossow,
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who provided key documents about the Interdata product line.
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09-Mar-06 RMS Increased register sets to architectural limit
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25-Jan-04 RMS Removed local logging support
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22-Sep-03 RMS Added additional instruction decode types
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21-Jun-03 RMS Changed subroutine argument for ARM compiler conflict
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@@ -65,9 +66,9 @@
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#if defined (IFP_IN_MEM)
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#define ReadFReg(r) (fp_in_hwre? \
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F[(r) >> 1]: ReadF (((r) << 1) & ~3, P))
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F[(r) >> 1]: ReadF (((r) << 1) & ~3, P))
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#define WriteFReg(r,v) if (fp_in_hwre) F[(r) >> 1] = (v); \
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else WriteF (((r) << 1) & ~3, (v), P)
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else WriteF (((r) << 1) & ~3, (v), P)
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#else
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#define ReadFReg(r) (F[(r) >> 1])
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#define WriteFReg(r,v) F[(r) >> 1] = (v)
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@@ -114,13 +115,11 @@ typedef struct {
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#define PSW_M_MAP 0xF
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#define PSW_MAP (PSW_M_MAP << PSW_V_MAP)
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#define PSW_V_REG 4 /* reg set, 32b */
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#define PSW_M_REG 0x1
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#define PSW_M_REG 0xF
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#define PSW_ID4 0xF40F /* I3, I4 PSW */
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#define PSW_x16 0xFF0F /* 7/16, 8/16 PSW */
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#define PSW_816E 0xFFFF /* 8/16E PSW */
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#define PSW_x32 0xFFFF /* 7/32, 8/32 PSW */
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#define PSW_GETMAP(x) (((x) >> PSW_V_MAP) & PSW_M_MAP)
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#define PSW_GETREG(x) (((x) >> PSW_V_REG) & PSW_M_REG)
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#define MCKOPSW 0x20 /* mchk old PSW, 32b */
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#define FPFPSW 0x28 /* flt fault PSW, 16b */
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@@ -655,7 +655,7 @@ sim> boot mt0
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Breakpoint, PC: 00A00 (B A5E)
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sim> d -w a10 0101 ; patch for TTY console
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sim> d -h a10 0202 ; patch for TTY console
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sim> att dm0 foo.dsk
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sim> att dm1 foo1.dsk
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sim> c
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@@ -904,4 +904,8 @@ Bugs found
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92. IDC: read with invalid head sets ACF, not DTE
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93. DP, IDC: write with cylinder overflow advanced selch pointer
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94. MT: read error must stop selector channel (if active)
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95. IDC: xx000000 to controller or drive are NOP's, not invalid commands
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96. IDC: WD/WH use standard Interdata write pointers
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97. SELCH: GO preserves EXA and SSTA
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98. CPU: DH overflow checking broken
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1054
Interdata/id_doc.txt
1054
Interdata/id_doc.txt
File diff suppressed because it is too large
Load Diff
@@ -505,7 +505,7 @@ if (OP_DPFP (op)) { /* double precision? */
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}
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else {
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WriteFReg (r1, hi);
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}
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}
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return cc;
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}
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@@ -527,6 +527,6 @@ if (OP_DPFP (op)) { /* double precision? */
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}
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else {
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WriteFReg (r1, fop->h);
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}
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}
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return cc;
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}
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@@ -1,6 +1,6 @@
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/* id_idc.c: Interdata MSM/IDC disk controller simulator
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Copyright (c) 2001-2005, Robert M. Supnik
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Copyright (c) 2001-2006, Robert M. Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -25,6 +25,8 @@
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idc MSM/IDC disk controller
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03-Apr-06 RMS Fixed WD/WH handling (found by Davis Johnson)
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30-Mar-06 RMS Fixed bug, nop command should be ignored (found by Davis Johnson)
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25-Apr-03 RMS Revised for extended file support
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16-Feb-03 RMS Fixed read to test transfer ok before selch operation
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@@ -199,14 +201,16 @@ extern uint32 int_req[INTSZ], int_enb[INTSZ];
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uint8 idcxb[IDC_NUMBY * 3]; /* xfer buffer */
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uint32 idc_bptr = 0; /* buffer ptr */
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uint32 idc_wdptr = 0; /* ctrl write data ptr */
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uint32 idc_db = 0; /* ctrl buffer */
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uint32 idd_db = 0; /* drive buffer */
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uint32 idc_sta = 0; /* ctrl status */
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uint32 idc_sec = 0; /* sector */
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uint32 idc_hcyl = 0; /* head/cyl */
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uint32 idc_svun = 0; /* most recent unit */
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uint32 idc_1st = 0; /* first byte */
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uint32 idc_arm = 0; /* ctrl armed */
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uint32 idd_db = 0; /* drive buffer */
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uint32 idd_wdptr = 0; /* drive write data ptr */
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uint32 idd_arm[ID_NUMDR] = { 0 }; /* drives armed */
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uint16 idd_dcy[ID_NUMDR] = { 0 }; /* desired cyl */
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uint32 idd_sirq = 0; /* drive saved irq */
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@@ -221,6 +225,7 @@ t_stat idc_svc (UNIT *uptr);
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t_stat idc_reset (DEVICE *dptr);
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t_stat idc_attach (UNIT *uptr, char *cptr);
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t_stat idc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);
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void idc_wd_byte (uint32 dat);
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t_stat idc_rds (UNIT *uptr);
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t_stat idc_wds (UNIT *uptr);
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t_bool idc_dter (UNIT *uptr, uint32 first);
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@@ -259,6 +264,8 @@ REG idc_reg[] = {
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{ BRDATA (DBUF, idcxb, 16, 8, IDC_NUMBY * 3) },
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{ HRDATA (DBPTR, idc_bptr, 10), REG_RO },
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{ FLDATA (FIRST, idc_1st, 0) },
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{ HRDATA (CWDPTR, idc_wdptr, 2) },
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{ HRDATA (DWDPTR, idc_wdptr, 1) },
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{ GRDATA (IREQ, int_req[l_IDC], 16, ID_NUMDR + 1, i_IDC) },
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{ GRDATA (IENB, int_enb[l_IDC], 16, ID_NUMDR + 1, i_IDC) },
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{ GRDATA (SIREQ, idd_sirq, 16, ID_NUMDR, i_IDC + 1), REG_RO },
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@@ -358,11 +365,12 @@ switch (op) { /* case IO op */
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return 0; /* return data */
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case IO_WD: /* write data */
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idc_sec = dat; /* sector */
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idc_wd_byte (dat); /* one byte only */
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break;
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case IO_WH: /* write halfword */
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idc_hcyl = dat; /* head/cylinder */
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idc_wd_byte (dat >> 8); /* high byte */
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idc_wd_byte (dat); /* low byte */
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break;
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case IO_SS: /* status */
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@@ -372,15 +380,17 @@ switch (op) { /* case IO op */
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case IO_OC: /* command */
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idc_arm = int_chg (v_IDC, dat, idc_arm); /* upd int ctrl */
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idc_wdptr = 0; /* init ptr */
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f = dat & CMC_MASK; /* get cmd */
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uptr = idc_dev.units + idc_svun; /* get unit */
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if (f & CMC_CLR) { /* clear? */
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idc_reset (&idc_dev); /* reset world */
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break;
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}
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if (!(idc_sta & STC_IDL) || /* if !idle, */
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sim_is_active (uptr) || /* unit busy, */
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(f == CMC_EXP0)) break; /* expg, ignore */
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if ((f == 0) || /* if nop, */
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(f == CMC_EXP0) || /* expg, */
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!(idc_sta & STC_IDL) || /* !idle, */
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sim_is_active (uptr)) break; /* unit busy, ignore */
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idc_sta = STA_BSY; /* bsy=1,idl,err=0 */
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idc_1st = 1; /* xfr not started */
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idc_bptr = 0; /* buffer empty */
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@@ -394,11 +404,37 @@ switch (op) { /* case IO op */
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return 0;
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}
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/* Process WD/WH data */
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void idc_wd_byte (uint32 dat)
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{
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dat = dat & 0xFF;
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switch (idc_wdptr) {
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case 0: /* byte 0 = sector */
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idc_sec = dat;
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idc_wdptr++;
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break;
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case 1: /* byte 1 = high hd/cyl */
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idc_hcyl = (idc_hcyl & 0xFF) | (dat << 8);
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idc_wdptr++;
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break;
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case 2: /* byte 2 = low hd/cyl */
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idc_hcyl = (idc_hcyl & 0xFF00) | dat;
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idc_wdptr = 0;
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break;
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}
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return;
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}
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/* Drives: IO routine */
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|
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uint32 id (uint32 dev, uint32 op, uint32 dat)
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{
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uint32 t, u;
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uint32 t, u, f;
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UNIT *uptr;
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if (dev == idc_dib.dno) return idc (dev, op, dat); /* controller? */
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@@ -408,15 +444,17 @@ switch (op) { /* case IO op */
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case IO_ADR: /* select */
|
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if (idc_sta & STC_IDL) idc_svun = u; /* idle? save unit */
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return HW; /* byte only */
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return BY; /* byte only */
|
||||
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case IO_RD: /* read data */
|
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case IO_RH:
|
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return 0;
|
||||
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case IO_WD: /* write data */
|
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case IO_WH: /* write halfword */
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idd_db = dat; /* save data */
|
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if (idd_wdptr & 1) /* low byte? */
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idd_db = (idd_db & 0xFF00) | dat;
|
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else idd_db = (idd_db & 0xFF) | (dat << 8); /* no, high */
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idd_wdptr = idd_wdptr ^ 1; /* other byte */
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break;
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||||
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case IO_SS: /* status */
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@@ -430,12 +468,15 @@ switch (op) { /* case IO op */
|
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|
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case IO_OC: /* command */
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idd_arm[u] = int_chg (v_IDC + u + 1, dat, idd_arm[u]);
|
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idd_wdptr = 0; /* init ptr */
|
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if (idd_arm[u] == 0) /* disarmed? */
|
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idd_sirq &= ~(1 << (v_IDC + u + 1)); /* clr saved req */
|
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if (sim_is_active (uptr) || /* if busy or */
|
||||
!(idc_sta & STC_IDL)) break; /* !idle, ignore */
|
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if ((dat & CMC_MASK) == CMDX_MASK) break; /* ignore 0x30 */
|
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uptr->FNC = (dat & CMC_MASK) | CMC_DRV; /* save cmd */
|
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f = dat & CMC_MASK; /* get cmd */
|
||||
if ((f == 0) || /* if nop, */
|
||||
(f == CMDX_MASK) || /* 0x30, */
|
||||
!(idc_sta & STC_IDL) || /* !idle, */
|
||||
sim_is_active (uptr)) break; /* unit busy, ignore */
|
||||
uptr->FNC = f | CMC_DRV; /* save cmd */
|
||||
idc_sta = idc_sta & ~STC_IDL; /* clr idle */
|
||||
sim_activate (uptr, idc_ctime); /* schedule */
|
||||
break;
|
||||
@@ -687,6 +728,8 @@ uint32 u;
|
||||
UNIT *uptr;
|
||||
|
||||
idc_sta = STC_IDL | STA_BSY; /* idle, busy */
|
||||
idc_wdptr = 0;
|
||||
idd_wdptr = 0;
|
||||
idc_1st = 0; /* clear flag */
|
||||
idc_svun = idc_db = 0; /* clear unit, buf */
|
||||
idc_sec = 0; /* clear addr */
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* id_io.c: Interdata CPU-independent I/O routines
|
||||
|
||||
Copyright (c) 2001-2005, Robert M. Supnik
|
||||
Copyright (c) 2001-2006, Robert M. Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
30-Mar-06 RMS Fixed bug, GO preserves EXA and SSTA (found by Davis Johnson)
|
||||
21-Jun-03 RMS Changed subroutine argument for ARM compiler conflict
|
||||
|
||||
Interdata I/O devices are defined by a device information block:
|
||||
@@ -209,7 +210,7 @@ switch (op) { /* case IO op */
|
||||
sch_wdc[ch] = 0;
|
||||
}
|
||||
else if (dat & SCHC_GO) { /* go? */
|
||||
sch_cmd[ch] = dat & (SCHC_GO | SCHC_RD);
|
||||
sch_cmd[ch] = dat & (SCHC_EXA | SCHC_SSTA| SCHC_GO | SCHC_RD);
|
||||
if (sch_wdc[ch] <= 4) { /* 4 bytes? */
|
||||
sch_sa[ch] = (sch_sa[ch] & PAMASK16) | bank; /* 16b addr */
|
||||
sch_ea[ch] = (sch_ea[ch] & PAMASK16) | bank;
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
/* id_mt.c: Interdata magnetic tape simulator
|
||||
|
||||
Copyright (c) 2001-2005, Robert M Supnik
|
||||
Copyright (c) 2001-2006, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@@ -25,6 +25,7 @@
|
||||
|
||||
mt M46-494 dual density 9-track magtape controller
|
||||
|
||||
16-Feb-06 RMS Added tape capacity checking
|
||||
18-Mar-05 RMS Added attached test to detach routine
|
||||
07-Dec-04 RMS Added read-only file support
|
||||
25-Apr-03 RMS Revised for extended file support
|
||||
@@ -153,6 +154,8 @@ MTAB mt_mod[] = {
|
||||
{ MTUF_WLK, MTUF_WLK, "write locked", "LOCKED", NULL },
|
||||
{ MTAB_XTD|MTAB_VUN, 0, "FORMAT", "FORMAT",
|
||||
&sim_tape_set_fmt, &sim_tape_show_fmt, NULL },
|
||||
{ MTAB_XTD|MTAB_VUN, 0, "CAPACITY", "CAPACITY",
|
||||
&sim_tape_set_capac, &sim_tape_show_capac, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",
|
||||
&set_dev, &show_dev, NULL },
|
||||
{ MTAB_XTD|MTAB_VDV, 0, "SELCH", "SELCH",
|
||||
@@ -260,6 +263,7 @@ uint32 i;
|
||||
int32 u = uptr - mt_dev.units;
|
||||
uint32 dev = mt_dib.dno + (u * o_MT0);
|
||||
t_mtrlnt tbc;
|
||||
t_bool passed_eot;
|
||||
t_stat st, r = SCPE_OK;
|
||||
|
||||
if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
|
||||
@@ -273,7 +277,7 @@ if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */
|
||||
|
||||
if (uptr->UCMD & MTC_STOP2) { /* stop, gen NMTN? */
|
||||
uptr->UCMD = 0; /* clr cmd */
|
||||
uptr->UST = STA_NMTN; /* set nmtn, not eot */
|
||||
uptr->UST = uptr->UST | STA_NMTN; /* set nmtn */
|
||||
mt_xfr = 0; /* clr xfr */
|
||||
if (mt_arm[u]) SET_INT (v_MT + u); /* set intr */
|
||||
return SCPE_OK;
|
||||
@@ -287,6 +291,7 @@ if (uptr->UCMD & MTC_STOP1) { /* stop, gen EOM? */
|
||||
return SCPE_OK;
|
||||
}
|
||||
|
||||
passed_eot = sim_tape_eot (uptr); /* passed EOT? */
|
||||
switch (uptr->UCMD) { /* case on function */
|
||||
|
||||
case MTC_REW: /* rewind */
|
||||
@@ -388,6 +393,8 @@ switch (uptr->UCMD) { /* case on function */
|
||||
break;
|
||||
} /* end case */
|
||||
|
||||
if (!passed_eot && sim_tape_eot (uptr)) /* just passed EOT? */
|
||||
uptr->UST = uptr->UST | STA_EOT;
|
||||
uptr->UCMD = uptr->UCMD | MTC_STOP1; /* set stop stage 1 */
|
||||
sim_activate (uptr, mt_rtime); /* schedule */
|
||||
return r;
|
||||
|
||||
Reference in New Issue
Block a user