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alpha: Fixed reversed definitions in opcode 12 (shifts)
It turns out that the two reversed opcodes Maurice identified were not the only problems in opcode 12 (shifts). All of the INS/EXT pairs at function codes .57 and above were reversed. In addition, the mnemonics in the opcode table in alpha_sys.c are wrong as well as reversed.
This commit is contained in:
Bob Supnik
committed by
Mark Pizzolato
Mark Pizzolato
parent
bbbe526f8c
commit
e12d500486
@@ -1,6 +1,6 @@
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/* alpha_cpu.c: Alpha CPU simulator
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Copyright (c) 2003-2006, Robert M Supnik
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Copyright (c) 2003-2017, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -23,6 +23,10 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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27-May-2017 RMS Fixed MIN/MAXx4 iteration counts (Mark Pizzolato)
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26-May-2017 RMS Fixed other reversed definitions in opcode 12
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28-Apr-2017 RMS Fixed reversed definitions of INSQH, EXTQH (Maurice Marks)
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Alpha architecturally-defined CPU state:
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PC<63:0> program counter
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@@ -41,7 +45,7 @@
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operating system to operating system. Alpha provides an intermediate layer
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of software (called PALcode) that implements the privileged state as well
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as a library of complex instruction functions. PALcode implementations
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are chip specific and system specific, as well as OS specific.
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are chip specific and system specific, as well as OS specific.14
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Alpha memory management is also "soft" and supported a variety of mapping
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schemes. VMS and Unix use a three level page table and directly expose
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@@ -216,8 +220,8 @@ extern t_uint64 op_lds (t_uint64 op);
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extern t_uint64 op_stf (t_uint64 op);
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extern t_uint64 op_stg (t_uint64 op);
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extern t_uint64 op_sts (t_uint64 op);
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extern t_uint64 vax_sqrt (uint32 ir, t_bool dp);
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extern t_uint64 ieee_sqrt (uint32 ir, t_bool dp);
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extern t_uint64 vax_sqrt (uint32 ir, uint32 dp);
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extern t_uint64 ieee_sqrt (uint32 ir, uint32 dp);
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extern void vax_fop (uint32 ir);
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extern void ieee_fop (uint32 ir);
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extern t_stat pal_19 (uint32 ir);
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@@ -227,7 +231,7 @@ extern t_stat pal_1e (uint32 ir);
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extern t_stat pal_1f (uint32 ir);
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extern t_uint64 trans_c (t_uint64 va);
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extern t_stat cpu_show_tlb (FILE *of, UNIT *uptr, int32 val, void *desc);
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extern t_stat pal_eval_intr (uint32 flag);
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extern uint32 pal_eval_intr (uint32 flag);
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extern t_stat pal_proc_excp (uint32 type);
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extern t_stat pal_proc_trap (uint32 type);
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extern t_stat pal_proc_intr (uint32 type);
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@@ -1074,46 +1078,46 @@ while (reason == 0) {
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res = byte_zap (R[ra], 0x3 >> sc);
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break;
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case 0x57: /* EXTWH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] << sc) & M16;
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break;
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case 0x5A: /* INSWH */
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case 0x57: /* INSWH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] & M16) >> sc;
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break;
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case 0x5A: /* EXTWH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] << sc) & M16;
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break;
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case 0x62: /* MSKLH */
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sc = 8 - (((uint32) rbv) & 7);
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res = byte_zap (R[ra], 0xF >> sc);
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break;
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case 0x67: /* EXTLH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] << sc) & M32;
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break;
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case 0x6A: /* INSLH */
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case 0x67: /* INSLH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] & M32) >> sc;
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break;
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case 0x6A: /* EXTLH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = (R[ra] << sc) & M32;
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break;
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case 0x72: /* MSKQH */
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sc = 8 - (((uint32) rbv) & 7);
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res = byte_zap (R[ra], 0xFF >> sc);
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break;
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case 0x77: /* EXTQH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = R[ra] << sc;
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break;
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case 0x7A: /* INSQH */
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case 0x77: /* INSQH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = R[ra] >> sc;
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break;
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case 0x7A: /* EXTQH */
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sc = (64 - (((uint32) rbv) << 3)) & 0x3F;
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res = R[ra] << sc;
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break;
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default:
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res = R[rc];
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break;
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@@ -1438,7 +1442,7 @@ while (reason == 0) {
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case 0x39: /* MINSW4 */
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if (!(arch_mask & AMASK_MVI)) ABORT (EXC_RSVI);
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for (i = 0, res = 0; i < 8; i = i++) {
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for (i = 0, res = 0; i < 4; i++) {
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s1 = SEXT_W_Q (R[ra] >> (i << 4));
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s2 = SEXT_W_Q (rbv >> (i << 4));
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res = res | (((s1 <= s2)? R[ra]: rbv) & word_mask[i]);
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@@ -1456,7 +1460,7 @@ while (reason == 0) {
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case 0x3B: /* MINUW4 */
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if (!(arch_mask & AMASK_MVI)) ABORT (EXC_RSVI);
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for (i = 0, res = 0; i < 8; i = i++) {
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for (i = 0, res = 0; i < 4; i++) {
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s64 = R[ra] & word_mask[i];
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t64 = rbv & word_mask[i];
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res = res | ((s64 <= t64)? s64: t64);
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@@ -1474,7 +1478,7 @@ while (reason == 0) {
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case 0x3D: /* MAXUW4 */
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if (!(arch_mask & AMASK_MVI)) ABORT (EXC_RSVI);
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for (i = 0, res = 0; i < 8; i = i++) {
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for (i = 0, res = 0; i < 4; i++) {
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s64 = R[ra] & word_mask[i];
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t64 = rbv & word_mask[i];
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res = res | ((s64 >= t64)? s64: t64);
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@@ -1492,7 +1496,7 @@ while (reason == 0) {
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case 0x3F: /* MAXSW4 */
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if (!(arch_mask & AMASK_MVI)) ABORT (EXC_RSVI);
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for (i = 0, res = 0; i < 8; i = i++) {
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for (i = 0, res = 0; i < 4; i++) {
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s1 = SEXT_W_Q (R[ra] >> (i << 4));
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s2 = SEXT_W_Q (rbv >> (i << 4));
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res = res | (((s1 >= s2)? R[ra]: rbv) & word_mask[i]);
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@@ -1841,7 +1845,7 @@ return SCPE_OK;
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t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
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{
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uint32 k, di, lnt;
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int32 k, di, lnt;
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char *cptr = (char *) desc;
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t_stat r;
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InstHistory *h;
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@@ -1,6 +1,6 @@
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/* alpha_sys.c: Alpha simulator interface
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Copyright (c) 2003-2006, Robert M Supnik
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Copyright (c) 2003-20017, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@@ -22,6 +22,8 @@
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Except as contained in this notice, the name of Robert M Supnik shall not be
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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26-May-17 RMS Fixed bad mnemonics and reversed definitions in opcode 12
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*/
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#include "alpha_defs.h"
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@@ -199,9 +201,9 @@ const char *opcode[] = {
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"MSKLL", "EXTLL", "INSLL",
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"ZAP", "ZAPNOT", "MSKQL", "SRL",
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"EXTQL", "SLL", "INSQL", "SRA",
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"MSKWQ", "EXTWQ", "INSWQ",
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"MSKLQ", "EXTLQ", "INSLQ",
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"MSKQH", "EXTQH", "INSQH",
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"MSKWH", "INSWH", "EXTWH",
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"MSKLH", "INSLH", "EXTLH",
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"MSKQH", "INSQH", "EXTQH",
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"MULL", "MULQ", "UMULH",
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"MULL/V", "MULLQ/V",
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"ITOFS", "ITOFF", "ITOFT",
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