diff --git a/CHANGES b/CHANGES
index fd22547..a0c97cf 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,5 +1,7 @@
xx.xx.20xx: Rhialto
version 0.8:
+ - Fixed immediate source operand of LDEXP, LD[IL][FD]
+ which is an integer, unlike several other FPP instructions.
19.03.2021: Rhialto
version 0.7:
diff --git a/assemble.c b/assemble.c
index 9a20625..a667526 100644
--- a/assemble.c
+++ b/assemble.c
@@ -1626,7 +1626,7 @@ static int assemble(
* Handbook describes it as a destination, and MACRO11 V05.05 doesn't
* allow a FP literal argument.
*/
- case OC_FPPSRC:
+ case OC_FPP_FSRC:
/* One fp immediate or a general addressing mode */ {
ADDR_MODE mode;
unsigned word;
@@ -1644,16 +1644,24 @@ static int assemble(
return CHECK_EOL;
#endif
- case OC_FPPGENAC:
+ case OC_FPP_SRCAC:
+ case OC_FPP_FSRCAC:
/* One gen and one reg 0-3 */ {
ADDR_MODE mode;
EX_TREE *value;
unsigned reg;
unsigned word;
- if (!get_fp_src_mode(cp, &cp, &mode)) {
- report(stack->top, "Invalid addressing mode (1st operand)\n");
- return 0;
+ if ((op->flags & OC_MASK) == OC_FPP_FSRCAC) {
+ if (!get_fp_src_mode(cp, &cp, &mode)) {
+ report(stack->top, "Invalid addressing mode (1st operand, fsrc)\n");
+ return 0;
+ }
+ } else {
+ if (!get_mode(cp, &cp, &mode)) {
+ report(stack->top, "Invalid addressing mode (1st operand)\n");
+ return 0;
+ }
}
cp = skipwhite(cp);
@@ -1684,8 +1692,8 @@ static int assemble(
}
return CHECK_EOL;
- case OC_FPPACGEN:
- /* One reg 0-3 and one gen */ {
+ case OC_FPP_ACFDST:
+ /* One reg 0-3 and one fdst */ {
ADDR_MODE mode;
EX_TREE *value;
unsigned reg;
diff --git a/symbols.c b/symbols.c
index c564b96..ec514c9 100644
--- a/symbols.c
+++ b/symbols.c
@@ -418,54 +418,54 @@ void add_symbols(
add_sym("WRTLCK", I_WRTLCK, OC_1GEN, &instruction_section, &system_st);
/* FPP instructions */
- add_sym("ABSD", I_ABSD, OC_FPPDST, &instruction_section, &system_st);
- add_sym("ABSF", I_ABSF, OC_FPPDST, &instruction_section, &system_st);
- add_sym("ADDD", I_ADDD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("ADDF", I_ADDF, OC_FPPGENAC, &instruction_section, &system_st);
+ add_sym("ABSD", I_ABSD, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("ABSF", I_ABSF, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("ADDD", I_ADDD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("ADDF", I_ADDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
add_sym("CFCC", I_CFCC, OC_NONE, &instruction_section, &system_st);
- add_sym("CLRD", I_CLRD, OC_FPPDST, &instruction_section, &system_st);
- add_sym("CLRF", I_CLRF, OC_FPPDST, &instruction_section, &system_st);
- add_sym("CMPD", I_CMPD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("CMPF", I_CMPF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("DIVD", I_DIVD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("DIVF", I_DIVF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCDF", I_LDCDF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCFD", I_LDCFD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCID", I_LDCID, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCIF", I_LDCIF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCLD", I_LDCLD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDCLF", I_LDCLF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDD", I_LDD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDEXP", I_LDEXP, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("LDF", I_LDF, OC_FPPGENAC, &instruction_section, &system_st);
+ add_sym("CLRD", I_CLRD, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("CLRF", I_CLRF, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("CMPD", I_CMPD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("CMPF", I_CMPF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("DIVD", I_DIVD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("DIVF", I_DIVF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("LDCDF", I_LDCDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("LDCFD", I_LDCFD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("LDCID", I_LDCID, OC_FPP_SRCAC, &instruction_section, &system_st);
+ add_sym("LDCIF", I_LDCIF, OC_FPP_SRCAC, &instruction_section, &system_st);
+ add_sym("LDCLD", I_LDCLD, OC_FPP_SRCAC, &instruction_section, &system_st);
+ add_sym("LDCLF", I_LDCLF, OC_FPP_SRCAC, &instruction_section, &system_st);
+ add_sym("LDD", I_LDD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("LDEXP", I_LDEXP, OC_FPP_SRCAC, &instruction_section, &system_st);
+ add_sym("LDF", I_LDF, OC_FPP_FSRCAC, &instruction_section, &system_st);
add_sym("LDFPS", I_LDFPS, OC_1GEN, &instruction_section, &system_st);
- add_sym("MODD", I_MODD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("MODF", I_MODF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("MULD", I_MULD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("MULF", I_MULF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("NEGD", I_NEGD, OC_FPPDST, &instruction_section, &system_st);
- add_sym("NEGF", I_NEGF, OC_FPPDST, &instruction_section, &system_st);
+ add_sym("MODD", I_MODD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("MODF", I_MODF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("MULD", I_MULD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("MULF", I_MULF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("NEGD", I_NEGD, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("NEGF", I_NEGF, OC_FPP_FDST, &instruction_section, &system_st);
add_sym("SETD", I_SETD, OC_NONE, &instruction_section, &system_st);
add_sym("SETF", I_SETF, OC_NONE, &instruction_section, &system_st);
add_sym("SETI", I_SETI, OC_NONE, &instruction_section, &system_st);
add_sym("SETL", I_SETL, OC_NONE, &instruction_section, &system_st);
add_sym("STA0", I_STA0, OC_NONE, &instruction_section, &system_st);
add_sym("STB0", I_STB0, OC_NONE, &instruction_section, &system_st);
- add_sym("STCDF", I_STCDF, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STCDI", I_STCDI, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STCDL", I_STCDL, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STCFD", I_STCFD, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STCFI", I_STCFI, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STCFL", I_STCFL, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STD", I_STD, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STEXP", I_STEXP, OC_FPPACGEN, &instruction_section, &system_st);
- add_sym("STF", I_STF, OC_FPPACGEN, &instruction_section, &system_st);
+ add_sym("STCDF", I_STCDF, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STCDI", I_STCDI, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STCDL", I_STCDL, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STCFD", I_STCFD, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STCFI", I_STCFI, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STCFL", I_STCFL, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STD", I_STD, OC_FPP_ACFDST, &instruction_section, &system_st);
+ add_sym("STEXP", I_STEXP, OC_FPP_ACDST, &instruction_section, &system_st);
+ add_sym("STF", I_STF, OC_FPP_ACFDST, &instruction_section, &system_st);
add_sym("STFPS", I_STFPS, OC_1GEN, &instruction_section, &system_st);
add_sym("STST", I_STST, OC_1GEN, &instruction_section, &system_st);
- add_sym("SUBD", I_SUBD, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("SUBF", I_SUBF, OC_FPPGENAC, &instruction_section, &system_st);
- add_sym("TSTD", I_TSTD, OC_FPPDST, &instruction_section, &system_st);
- add_sym("TSTF", I_TSTF, OC_FPPDST, &instruction_section, &system_st);
+ add_sym("SUBD", I_SUBD, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("SUBF", I_SUBF, OC_FPP_FSRCAC, &instruction_section, &system_st);
+ add_sym("TSTD", I_TSTD, OC_FPP_FDST, &instruction_section, &system_st);
+ add_sym("TSTF", I_TSTF, OC_FPP_FDST, &instruction_section, &system_st);
/* The CIS instructions */
add_sym("ADDNI", I_ADDN|I_CIS_I, OC_CIS3, &instruction_section, &system_st);
diff --git a/symbols.h b/symbols.h
index 9b5e6d3..afcdd7b 100644
--- a/symbols.h
+++ b/symbols.h
@@ -312,19 +312,22 @@ enum operand_codes { OC_MASK = 0xff00,
/* FADD, FSUB, FMUL, FDIV, RTS */
OC_SOB = 0x0800,
/* SOB */
- OC_FPPGENAC = 0x0900,
- /* FPP (gen, floating ac 0-3) */
- OC_FPPACGEN = 0x0a00,
- /* FPP (floating ac 0-3, gen) */
- OC_FPPSRC = 0x0b00,
- /* FPP fp source: immediate or gen */
- OC_FPPDST = OC_1GEN,
- /* FPP general destination */
- OC_CIS2 = 0x0c00,
+ OC_FPP_FSRCAC = 0x0900,
+ /* FPP (fsrc gen, floating ac 0-3) */
+ OC_FPP_SRCAC = 0x0a00,
+ /* FPP (src gen, floating ac 0-3) */
+ OC_FPP_ACFDST = 0x0b00,
+ OC_FPP_ACDST = OC_FPP_ACFDST,
+ /* FPP (floating ac 0-3, fdst gen) */
+ /* OC_FPP_FSRC = 0x0c00, */
+ /* FPP fp source: immediate or fsrc gen */
+ OC_FPP_FDST = OC_1GEN,
+ /* FPP fdst general destination */
+ OC_CIS2 = 0x0d00,
/* CIS with 2 parameter words */
- OC_CIS3 = 0x0d00,
+ OC_CIS3 = 0x0e00,
/* CIS with 3 parameter words */
- OC_CIS4 = 0x0e00,
+ OC_CIS4 = 0x0f00,
/* CIS with 4 parameter words */
OC__LAST = 0xff00
};
diff --git a/tests/test-float.lst.ok b/tests/test-float.lst.ok
index ec5a5b0..bb1e919 100644
--- a/tests/test-float.lst.ok
+++ b/tests/test-float.lst.ok
@@ -137,31 +137,74 @@
114 000370 172227 041040 addf #^O41040,F2 ; taken literally
115 000374 172127 040200 addf #1,ac1 ; as float
116 000400 172127 040200 addf #1.,ac1 ; as float
- 117 000404 172127 000001 addf #^D1,ac1 ; literally
- 118 000410 172127 000002 addf #<1+1>,ac1 ; literally
- 119 000414 172127 040300 addf #1.5,ac1 ; as float
- 120 000420 172127 140263 addd #-1.4,ac1 ; as float
- 121
- 122 ; TODO: let parser check for junk at end of line
-test-float.mac:123: ***ERROR Junk at end of line ('5 ; bad: ')
- 123 000424 170627 000002 absf #2.5 ; bad: operand is destination
-test-float.mac:124: ***ERROR Junk at end of line ('5 ; bad: ')
- 124 000430 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
-test-float.mac:125: ***ERROR Junk at end of line ('5 ; bad: junk')
- 125 000434 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
- 126 000440 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
- 127
- 128
- 129 .end
- 129
+ 117 000404 172127 040200 addf #1.0,ac1 ; as float
+ 118 000410 172127 000001 addf #^D1,ac1 ; literally
+ 119 000414 173027 000001 subf #<1>,ac0 ; literally
+ 120 000420 172127 000002 addf #<1+1>,ac1 ; literally
+test-float.mac:121: ***ERROR Invalid addressing mode (1st operand, fsrc)
+ 121 subf #<1.0>,ac0 ; error
+ 122 000424 172127 040300 addf #1.5,ac1 ; as float
+ 123 000430 172127 140263 addd #-1.4,ac1 ; as float
+ 124 000434 173027 040200 subf #<^F 1.0>,ac0 ; as float
+test-float.mac:125: ***ERROR Invalid addressing mode (1st operand, fsrc)
+ 125 subf #<^D 1.0>,ac0 ; error
+ 126 000440 173027 000001 subf #<^D 1>,ac0 ; literally
+ 127 000444 173027 000002 subf #^D<1+1>,ac0 ; literally
+ 128 000450 173027 000002 subf #^D 1+1 ,ac0 ; literally
+ 129 000454 173027 042572 subf #1e3,ac0 ; as float
+test-float.mac:130: ***ERROR Invalid syntax (comma expected)
+ 130 subf #1e 3,ac0 ; TODO: accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
+ 131 000001 a = 1
+ 132 000003 e3 = 3
+ 133 000460 173027 000001 subf #a,ac0 ; a interpreted as bit pattern
+ 134 000464 173027 000001 subf #,ac0 ; a interpreted as bit pattern
+ 135 000470 173027 000003 subf #e3,ac0 ; e3 is the label
+test-float.mac:136: ***ERROR Invalid addressing mode (1st operand, fsrc)
+ 136 subf #<1e3>,ac0 ; error N
+ 137
+test-float.mac:138: ***ERROR Junk at end of line ('5 ; bad: ')
+ 138 000474 170627 000002 absf #2.5 ; bad: operand is destination
+test-float.mac:139: ***ERROR Junk at end of line ('5 ; bad: ')
+ 139 000500 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
+test-float.mac:140: ***ERROR Junk at end of line ('5 ; bad: junk')
+ 140 000504 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
+ 141 000510 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
+ 142
+ 143 ; Test immediate source argument for instructions that have one (src or fsrc)
+ 144
+ 145 000514 172027 040200 addd #1,ac0 ; float
+ 146 000520 172027 040200 addf #1,ac0 ; float
+ 147 000524 173427 040200 cmpd #1,ac0 ; float
+ 148 000530 173427 040200 cmpf #1,ac0 ; float
+ 149 000534 174427 040200 divd #1,ac0 ; float
+ 150 000540 174427 040200 divf #1,ac0 ; float
+ 151 000544 177427 040200 ldcdf #1,ac0 ; float
+ 152 000550 177427 040200 ldcfd #1,ac0 ; float
+ 153 000554 177027 000001 ldcid #1,ac0 ; integer
+ 154 000560 177027 000001 ldcif #1,ac0 ; integer
+ 155 000564 177027 000001 ldcld #1,ac0 ; integer
+ 156 000570 177027 000001 ldclf #1,ac0 ; integer
+ 157 000574 172427 040200 ldd #1,ac0 ; float
+ 158 000600 172427 040200 ldf #1,ac0 ; float
+ 159 000604 176427 000001 ldexp #1,ac0 ; integer
+ 160 000610 171427 040200 modd #1,ac0 ; float
+ 161 000614 171427 040200 modf #1,ac0 ; float
+ 162 000620 171027 040200 muld #1,ac0 ; float
+ 163 000624 171027 040200 mulf #1,ac0 ; float
+ 164 000630 173027 040200 subd #1,ac0 ; float
+ 165 000634 173027 040200 subf #1,ac0 ; float
+ 166
+ 167 .end
+ 167
Symbol table
-. ******R 001 AC0 =%000000 AC1 =%000001 F2 =%000002
+. ******R 001 AC0 =%000000 E3 = 000003
+A = 000001 AC1 =%000001 F2 =%000002
Program sections:
. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV)
- 000444 001 (RW,I,LCL,REL,CON,NOSAV)
+ 000640 001 (RW,I,LCL,REL,CON,NOSAV)
diff --git a/tests/test-float.mac b/tests/test-float.mac
index 97b6eae..98d420a 100644
--- a/tests/test-float.mac
+++ b/tests/test-float.mac
@@ -114,16 +114,54 @@ f2 = %2
addf #^O41040,F2 ; taken literally
addf #1,ac1 ; as float
addf #1.,ac1 ; as float
+ addf #1.0,ac1 ; as float
addf #^D1,ac1 ; literally
+ subf #<1>,ac0 ; literally
addf #<1+1>,ac1 ; literally
+ subf #<1.0>,ac0 ; error
addf #1.5,ac1 ; as float
addd #-1.4,ac1 ; as float
+ subf #<^F 1.0>,ac0 ; as float
+ subf #<^D 1.0>,ac0 ; error
+ subf #<^D 1>,ac0 ; literally
+ subf #^D<1+1>,ac0 ; literally
+ subf #^D 1+1 ,ac0 ; literally
+ subf #1e3,ac0 ; as float
+ subf #1e 3,ac0 ; TODO: accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
+a = 1
+e3 = 3
+ subf #a,ac0 ; a interpreted as bit pattern
+ subf #,ac0 ; a interpreted as bit pattern
+ subf #e3,ac0 ; e3 is the label
+ subf #<1e3>,ac0 ; error N
- ; TODO: let parser check for junk at end of line
absf #2.5 ; bad: operand is destination
tstd #2.5 ; bad: operand is considered FDST by the arch handbook
stf ac0,#2.5 ; bad: junk at end of line
stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
+ ; Test immediate source argument for instructions that have one (src or fsrc)
+
+ addd #1,ac0 ; float
+ addf #1,ac0 ; float
+ cmpd #1,ac0 ; float
+ cmpf #1,ac0 ; float
+ divd #1,ac0 ; float
+ divf #1,ac0 ; float
+ ldcdf #1,ac0 ; float
+ ldcfd #1,ac0 ; float
+ ldcid #1,ac0 ; integer
+ ldcif #1,ac0 ; integer
+ ldcld #1,ac0 ; integer
+ ldclf #1,ac0 ; integer
+ ldd #1,ac0 ; float
+ ldf #1,ac0 ; float
+ ldexp #1,ac0 ; integer
+ modd #1,ac0 ; float
+ modf #1,ac0 ; float
+ muld #1,ac0 ; float
+ mulf #1,ac0 ; float
+ subd #1,ac0 ; float
+ subf #1,ac0 ; float
.end
diff --git a/tests/test-operands.lst.ok b/tests/test-operands.lst.ok
index e772380..a6e8345 100644
--- a/tests/test-operands.lst.ok
+++ b/tests/test-operands.lst.ok
@@ -118,9 +118,9 @@ test-operands.mac:75: ***ERROR Invalid addressing mode (2nd operand: register ex
test-operands.mac:86: ***ERROR Junk at end of line (',ac1 ; bad
')
86 000112 171111 mulf (r1),ac1,ac1 ; bad
-test-operands.mac:87: ***ERROR Invalid addressing mode (1st operand)
+test-operands.mac:87: ***ERROR Invalid addressing mode (1st operand, fsrc)
87 mulf ; bad
-test-operands.mac:88: ***ERROR Invalid addressing mode (1st operand)
+test-operands.mac:88: ***ERROR Invalid addressing mode (1st operand, fsrc)
88 mulf ( ; bad
test-operands.mac:89: ***ERROR Invalid syntax (comma expected)
89 mulf (r1) ; bad