mirror of
https://github.com/open-simh/simtools.git
synced 2026-04-25 03:34:32 +00:00
Add some FP test cases, including some parse errors.
Adjust the parsing a bit, and generate 0 values for bad syntax like the reference version does.
This commit is contained in:
Olaf Seibert
37
assemble.c
37
assemble.c
@@ -71,7 +71,20 @@ static int assemble(
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op = get_op(cp, &cp); /* Look at operation code */
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op = get_op(cp, &cp); /* Look at operation code */
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/* FIXME: this code will blindly look into .REM commentary and
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/* FIXME: this code will blindly look into .REM commentary and
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find operation codes. Incidentally, so will read_body. */
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find operation codes. Incidentally, so will read_body().
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That doesn't really matter, though, since the original also
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did that (line 72 ends the suppressed conditional block):
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69 .if NE,0
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70 .rem &
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71 junk
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72 .endc
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A 73 000144 000000G 000000G more junk
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A 74 000150 000000G 000000G 000000G line that ends the comments with &
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000156 000000G 000000G 000000C
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O 75 .endc
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*/
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if (op == NULL)
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if (op == NULL)
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return 1; /* Not found. Don't care. */
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return 1; /* Not found. Don't care. */
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@@ -341,20 +354,24 @@ static int assemble(
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{
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{
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int ok = 1;
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int ok = 1;
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while (!EOL(*cp)) {
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while (ok && !EOL(*cp)) {
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unsigned flt[4];
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unsigned flt[4];
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if (parse_float(cp, &cp, (op->value == P_FLT4 ? 4 : 2), flt)) {
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if (parse_float(cp, &cp, (op->value == P_FLT4 ? 4 : 2), flt)) {
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/* Store the word values */
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/* All is well */
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store_word(stack->top, tr, 2, flt[0]);
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store_word(stack->top, tr, 2, flt[1]);
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if (op->value == P_FLT4) {
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store_word(stack->top, tr, 2, flt[2]);
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store_word(stack->top, tr, 2, flt[3]);
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}
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} else {
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} else {
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report(stack->top, "Bad floating point format\n");
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report(stack->top, "Bad floating point format\n");
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ok = 0;
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ok = 0; /* Don't try to parse the rest of the line */
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flt[0] = flt[1] /* Store zeroes */
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= flt[2]
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= flt[3] = 0;
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}
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/* Store the word values */
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store_word(stack->top, tr, 2, flt[0]);
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store_word(stack->top, tr, 2, flt[1]);
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if (op->value == P_FLT4) {
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store_word(stack->top, tr, 2, flt[2]);
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store_word(stack->top, tr, 2, flt[3]);
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}
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}
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cp = skipdelim(cp);
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cp = skipdelim(cp);
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}
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}
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2
parse.c
2
parse.c
@@ -662,7 +662,7 @@ int parse_float(
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}
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}
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DF("float_sign: %d\n", float_sign);
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DF("float_sign: %d\n", float_sign);
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for (;;) {
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while (!EOL(*cp)) {
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if (isdigit(*cp)) {
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if (isdigit(*cp)) {
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/* Can we multiply by 10? */
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/* Can we multiply by 10? */
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DF("digit: %c\n", *cp);
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DF("digit: %c\n", *cp);
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@@ -121,89 +121,178 @@
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99 000340 077777 177777 177777 .FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
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99 000340 077777 177777 177777 .FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
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000346 177777
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000346 177777
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100
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100
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101 ; Several ways to define a name for the fpp registers
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101 000350 040200 000000 000000 .flt4 1.0000000000000000138777878078144567552953958511353 ; 0040200 0000000 0000000 0000000
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102
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000356 000000
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103 000000 ac0 = r0
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102 000360 040200 000000 000000 .flt4 1.0000000000000000416333634234433702658861875534058 ; 0040200 0000000 0000000 0000001
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104 000001 ac1 = %1
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000366 000001
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105 000002 f2 = %2
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103 000370 040177 177777 177777 .flt4 0.99999999999999997918331828827831486705690622329712 ; 0040177 0177777 0177777 0177776
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106
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000376 177776
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107 000350 171003 mulf r3,ac0
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104 000400 040177 177777 177777 .flt4 0.99999999999999999306110609609277162235230207443237 ; 0040177 0177777 0177777 0177777
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108 000352 171102 mulf r2,ac1
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000406 177777
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109 000354 172227 041040 ADDF #^O41040,F2
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105
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110 000360 172127 040200 addf #1,ac1
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106 000410 040200 000000 000000 .flt4 100E-2 ; 040200 000000 000000 000000
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111
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000416 000000
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112 000364 171003 mulf r3,ac0
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107 000420 044303 050000 000000 .flt4 1.0E5 ; 044303 050000 000000 000000
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113 000366 171102 mulf r2,ac1
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000426 000000
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114 000370 172227 041040 addf #^O41040,F2 ; taken literally
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108 000430 050425 001371 000000 .flt4 1.0E10 ; 050425 001371 000000 000000
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115 000374 172127 040200 addf #1,ac1 ; as float
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000436 000000
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116 000400 172127 040200 addf #1.,ac1 ; as float
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109 000440 060655 074353 142654 .flt4 1.0E20 ; 060655 074353 142654 061000
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117 000404 172127 040200 addf #1.0,ac1 ; as float
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000446 061000
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118 000410 172127 000001 addf #^D1,ac1 ; literally
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110 000450 071111 171311 146404 .flt4 1.0E30 ; 071111 171311 146404 063517
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119 000414 173027 000001 subf #<1>,ac0 ; literally
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000456 063517
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120 000420 172127 000002 addf #<1+1>,ac1 ; literally
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111 000460 077626 073231 050265 .flt4 1.0E38 ; 077626 073231 050265 006611
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test-float.mac:121: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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000466 006611
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121 subf #<1.0>,ac0 ; error
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112
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122 000424 172127 040300 addf #1.5,ac1 ; as float
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113 000470 034047 142654 043433 .flt4 1.0E-5 ; 034047 142654 043433 043604
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123 000430 172127 140263 addd #-1.4,ac1 ; as float
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000476 043604
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124 000434 173027 040200 subf #<^F 1.0>,ac0 ; as float
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114 000500 027733 163376 147275 .flt4 1.0E-10 ; 027733 163376 147275 166726
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test-float.mac:125: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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000506 166726
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125 subf #<^D 1.0>,ac0 ; error
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115 000510 017474 162410 062222 .flt4 1.0E-20 ; 017474 162410 062222 010433
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126 000440 173027 000001 subf #<^D 1>,ac0 ; literally
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000516 010433
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127 000444 173027 000002 subf #^D<1+1>,ac0 ; literally
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116 000520 007242 041137 173536 .flt4 1.0E-30 ; 007242 041137 173536 012374
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128 000450 173027 000002 subf #^D 1+1 ,ac0 ; literally
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000526 012374
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129 000454 173027 042572 subf #1e3,ac0 ; as float
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117 000530 000531 143734 166523 .flt4 1.0E-38 ; 000531 143734 166523 143442
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130 000460 173027 042572 subf #1e 3,ac0 ; accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
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000536 143442
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131 000001 a = 1
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118
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132 000003 e3 = 3
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119 000540 057514 054000 000000 .flt4 3681129745421959167 ; 057514 054000 000000 000000
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133 000464 173027 000001 subf #a,ac0 ; a interpreted as bit pattern
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000546 000000
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134 000470 173027 000001 subf #<a>,ac0 ; a interpreted as bit pattern
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120 000550 057514 054000 000000 .flt4 3681129745421959168 ; 0x3316000000000000 057514 054000 000000 000000
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135 000474 173027 000003 subf #e3,ac0 ; e3 is the label
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000556 000000
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test-float.mac:136: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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121 000560 057514 054000 000000 .flt4 3681129745421959169 ; 057514 054000 000000 000000
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136 subf #<1e3>,ac0 ; error N
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000566 000000
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137
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122 000570 057514 054000 000000 .flt4 3681129745421959170 ; 057514 054000 000000 000000
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test-float.mac:138: ***ERROR Junk at end of line ('5 ; bad: ')
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000576 000000
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138 000500 170627 000002 absf #2.5 ; bad: operand is destination
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123
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test-float.mac:139: ***ERROR Junk at end of line ('5 ; bad: ')
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124 000600 060114 146000 000000 .flt4 14757170078986272767 ; 060114 146000 000000 000000
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139 000504 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
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000606 000000
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test-float.mac:140: ***ERROR Junk at end of line ('5 ; bad: junk')
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125 000610 060114 146000 000000 .flt4 14757170078986272768 ; 0xCCCC000000000000 060114 146000 000000 000000
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140 000510 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
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000616 000000
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141 000514 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
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126 000620 060114 146000 000000 .flt4 14757170078986272769 ; 060114 146000 000000 000000
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142
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000626 000000
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143 ; Test immediate source argument for instructions that have one (src or fsrc)
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127 000630 060114 146000 000000 .flt4 14757170078986272780 ; 060114 146000 000000 000000
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144
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000636 000000
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145 000520 172027 040200 addd #1,ac0 ; float
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128
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146 000524 172027 040200 addf #1,ac0 ; float
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129 000640 040511 007732 121041 .flt4 3.1415926535897932384626433 ; 040511 007732 121041 064302
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147 000530 173427 040200 cmpd #1,ac0 ; float
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000646 064302
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148 000534 173427 040200 cmpf #1,ac0 ; float
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130
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149 000540 174427 040200 divd #1,ac0 ; float
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131 ; Try some possibly incomplete numbers
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150 000544 174427 040200 divf #1,ac0 ; float
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132
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151 000550 177427 040200 ldcdf #1,ac0 ; float
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test-float.mac:133: ***ERROR Bad floating point format
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152 000554 177427 040200 ldcfd #1,ac0 ; float
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133 000650 000000 000000 000000 .flt4 + ; bad
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153 000560 177027 000001 ldcid #1,ac0 ; integer
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000656 000000
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154 000564 177027 000001 ldcif #1,ac0 ; integer
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134 000660 040200 000000 000000 .flt4 +1 ; ok
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155 000570 177027 000001 ldcld #1,ac0 ; integer
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000666 000000
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156 000574 177027 000001 ldclf #1,ac0 ; integer
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test-float.mac:135: ***ERROR Bad floating point format
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157 000600 172427 040200 ldd #1,ac0 ; float
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135 000670 000000 000000 000000 .flt4 +E1 ; bad
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158 000604 172427 040200 ldf #1,ac0 ; float
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000676 000000
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159 000610 176427 000001 ldexp #1,ac0 ; integer
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test-float.mac:136: ***ERROR Bad floating point format
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160 000614 171427 040200 modd #1,ac0 ; float
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136 000700 000000 000000 000000 .flt4 - ; bad
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161 000620 171427 040200 modf #1,ac0 ; float
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000706 000000
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162 000624 171027 040200 muld #1,ac0 ; float
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137 000710 140200 000000 000000 .flt4 -1 ; ok
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163 000630 171027 040200 mulf #1,ac0 ; float
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000716 000000
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164 000634 173027 040200 subd #1,ac0 ; float
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138 000720 140200 000000 000000 .flt4 -1. ; ok
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165 000640 173027 040200 subf #1,ac0 ; float
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000726 000000
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166
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test-float.mac:139: ***ERROR Bad floating point format
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167 .end
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139 000730 000000 000000 000000 .flt4 -1.. ; bad
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167
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000736 000000
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test-float.mac:140: ***ERROR Bad floating point format
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140 000740 000000 000000 000000 .flt4 -E1 ; bad
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000746 000000
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141 000750 000000 000000 000000 .flt4 +. ; bad
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000756 000000
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142 000760 000000 000000 000000 .flt4 -. ; bad
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000766 000000
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143 000770 000000 000000 000000 .flt4 . ; bad
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000776 000000
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test-float.mac:144: ***ERROR Bad floating point format
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144 001000 000000 000000 000000 .flt4 .. ; bad
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001006 000000
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145 001010 000000 000000 000000 .flt4 .E10 ; bad
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001016 000000
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146
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147 ; Several ways to define a name for the fpp registers
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148
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149 000000 ac0 = r0
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150 000001 ac1 = %1
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151 000002 f2 = %2
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|
152
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153 001020 171003 mulf r3,ac0
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154 001022 171102 mulf r2,ac1
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155 001024 172227 041040 ADDF #^O41040,F2
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|
156 001030 172127 040200 addf #1,ac1
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|
157
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158 001034 171003 mulf r3,ac0
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159 001036 171102 mulf r2,ac1
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|
160 001040 172227 041040 addf #^O41040,F2 ; taken literally
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161 001044 172127 040200 addf #1,ac1 ; as float
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162 001050 172127 040200 addf #1.,ac1 ; as float
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163 001054 172127 040200 addf #1.0,ac1 ; as float
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|
164 001060 172127 000001 addf #^D1,ac1 ; literally
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|
165 001064 173027 000001 subf #<1>,ac0 ; literally
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|
166 001070 172127 000002 addf #<1+1>,ac1 ; literally
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test-float.mac:167: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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|
167 subf #<1.0>,ac0 ; error
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|
168 001074 172127 040300 addf #1.5,ac1 ; as float
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|
169 001100 172127 140263 addd #-1.4,ac1 ; as float
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|
170 001104 173027 040200 subf #<^F 1.0>,ac0 ; as float
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|
test-float.mac:171: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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|
171 subf #<^D 1.0>,ac0 ; error
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|
172 001110 173027 000001 subf #<^D 1>,ac0 ; literally
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|
173 001114 173027 000002 subf #^D<1+1>,ac0 ; literally
|
||||||
|
174 001120 173027 000002 subf #^D 1+1 ,ac0 ; literally
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||||||
|
175 001124 173027 042572 subf #1e3,ac0 ; as float
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||||||
|
176 001130 173027 042572 subf #1e 3,ac0 ; accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
|
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|
177 000001 a = 1
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|
178 000003 e3 = 3
|
||||||
|
179 001134 173027 000001 subf #a,ac0 ; a interpreted as bit pattern
|
||||||
|
180 001140 173027 000001 subf #<a>,ac0 ; a interpreted as bit pattern
|
||||||
|
181 001144 173027 000003 subf #e3,ac0 ; e3 is the label
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||||||
|
test-float.mac:182: ***ERROR Invalid addressing mode (1st operand, fsrc: Invalid expression after '#')
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||||||
|
182 subf #<1e3>,ac0 ; error N
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|
183
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||||||
|
test-float.mac:184: ***ERROR Junk at end of line ('5 ; bad: ')
|
||||||
|
184 001150 170627 000002 absf #2.5 ; bad: operand is destination
|
||||||
|
test-float.mac:185: ***ERROR Junk at end of line ('5 ; bad: ')
|
||||||
|
185 001154 170527 000002 tstd #2.5 ; bad: operand is considered FDST by the arch handbook
|
||||||
|
test-float.mac:186: ***ERROR Junk at end of line ('5 ; bad: junk')
|
||||||
|
186 001160 174027 000002 stf ac0,#2.5 ; bad: junk at end of line
|
||||||
|
187 001164 174027 000002 stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
|
||||||
|
188
|
||||||
|
189 ; Test immediate source argument for instructions that have one (src or fsrc)
|
||||||
|
190
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||||||
|
191 001170 172027 040200 addd #1,ac0 ; float
|
||||||
|
192 001174 172027 040200 addf #1,ac0 ; float
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||||||
|
193 001200 173427 040200 cmpd #1,ac0 ; float
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||||||
|
194 001204 173427 040200 cmpf #1,ac0 ; float
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||||||
|
195 001210 174427 040200 divd #1,ac0 ; float
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||||||
|
196 001214 174427 040200 divf #1,ac0 ; float
|
||||||
|
197 001220 177427 040200 ldcdf #1,ac0 ; float
|
||||||
|
198 001224 177427 040200 ldcfd #1,ac0 ; float
|
||||||
|
199 001230 177027 000001 ldcid #1,ac0 ; integer
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||||||
|
200 001234 177027 000001 ldcif #1,ac0 ; integer
|
||||||
|
201 001240 177027 000001 ldcld #1,ac0 ; integer
|
||||||
|
202 001244 177027 000001 ldclf #1,ac0 ; integer
|
||||||
|
203 001250 172427 040200 ldd #1,ac0 ; float
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||||||
|
204 001254 172427 040200 ldf #1,ac0 ; float
|
||||||
|
205 001260 176427 000001 ldexp #1,ac0 ; integer
|
||||||
|
206 001264 171427 040200 modd #1,ac0 ; float
|
||||||
|
207 001270 171427 040200 modf #1,ac0 ; float
|
||||||
|
208 001274 171027 040200 muld #1,ac0 ; float
|
||||||
|
209 001300 171027 040200 mulf #1,ac0 ; float
|
||||||
|
210 001304 173027 040200 subd #1,ac0 ; float
|
||||||
|
211 001310 173027 040200 subf #1,ac0 ; float
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||||||
|
212
|
||||||
|
213 .end
|
||||||
|
213
|
||||||
|
|
||||||
|
|
||||||
Symbol table
|
Symbol table
|
||||||
|
|
||||||
. 000644R 001 AC0 =%000000 E3 = 000003
|
. 001314R 001 AC0 =%000000 E3 = 000003
|
||||||
A = 000001 AC1 =%000001 F2 =%000002
|
A = 000001 AC1 =%000001 F2 =%000002
|
||||||
|
|
||||||
|
|
||||||
Program sections:
|
Program sections:
|
||||||
|
|
||||||
. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV)
|
. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV)
|
||||||
000644 001 (RW,I,LCL,REL,CON,NOSAV)
|
001314 001 (RW,I,LCL,REL,CON,NOSAV)
|
||||||
|
|||||||
@@ -98,6 +98,52 @@
|
|||||||
.FLT4 170141183460469230564930741053754966015 ; 2**127-(2**70-2**64+2**62+1)
|
.FLT4 170141183460469230564930741053754966015 ; 2**127-(2**70-2**64+2**62+1)
|
||||||
.FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
|
.FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
|
||||||
|
|
||||||
|
.flt4 1.0000000000000000138777878078144567552953958511353 ; 0040200 0000000 0000000 0000000
|
||||||
|
.flt4 1.0000000000000000416333634234433702658861875534058 ; 0040200 0000000 0000000 0000001
|
||||||
|
.flt4 0.99999999999999997918331828827831486705690622329712 ; 0040177 0177777 0177777 0177776
|
||||||
|
.flt4 0.99999999999999999306110609609277162235230207443237 ; 0040177 0177777 0177777 0177777
|
||||||
|
|
||||||
|
.flt4 100E-2 ; 040200 000000 000000 000000
|
||||||
|
.flt4 1.0E5 ; 044303 050000 000000 000000
|
||||||
|
.flt4 1.0E10 ; 050425 001371 000000 000000
|
||||||
|
.flt4 1.0E20 ; 060655 074353 142654 061000
|
||||||
|
.flt4 1.0E30 ; 071111 171311 146404 063517
|
||||||
|
.flt4 1.0E38 ; 077626 073231 050265 006611
|
||||||
|
|
||||||
|
.flt4 1.0E-5 ; 034047 142654 043433 043604
|
||||||
|
.flt4 1.0E-10 ; 027733 163376 147275 166726
|
||||||
|
.flt4 1.0E-20 ; 017474 162410 062222 010433
|
||||||
|
.flt4 1.0E-30 ; 007242 041137 173536 012374
|
||||||
|
.flt4 1.0E-38 ; 000531 143734 166523 143442
|
||||||
|
|
||||||
|
.flt4 3681129745421959167 ; 057514 054000 000000 000000
|
||||||
|
.flt4 3681129745421959168 ; 0x3316000000000000 057514 054000 000000 000000
|
||||||
|
.flt4 3681129745421959169 ; 057514 054000 000000 000000
|
||||||
|
.flt4 3681129745421959170 ; 057514 054000 000000 000000
|
||||||
|
|
||||||
|
.flt4 14757170078986272767 ; 060114 146000 000000 000000
|
||||||
|
.flt4 14757170078986272768 ; 0xCCCC000000000000 060114 146000 000000 000000
|
||||||
|
.flt4 14757170078986272769 ; 060114 146000 000000 000000
|
||||||
|
.flt4 14757170078986272780 ; 060114 146000 000000 000000
|
||||||
|
|
||||||
|
.flt4 3.1415926535897932384626433 ; 040511 007732 121041 064302
|
||||||
|
|
||||||
|
; Try some possibly incomplete numbers
|
||||||
|
|
||||||
|
.flt4 + ; bad
|
||||||
|
.flt4 +1 ; ok
|
||||||
|
.flt4 +E1 ; bad
|
||||||
|
.flt4 - ; bad
|
||||||
|
.flt4 -1 ; ok
|
||||||
|
.flt4 -1. ; ok
|
||||||
|
.flt4 -1.. ; bad
|
||||||
|
.flt4 -E1 ; bad
|
||||||
|
.flt4 +. ; bad
|
||||||
|
.flt4 -. ; bad
|
||||||
|
.flt4 . ; bad
|
||||||
|
.flt4 .. ; bad
|
||||||
|
.flt4 .E10 ; bad
|
||||||
|
|
||||||
; Several ways to define a name for the fpp registers
|
; Several ways to define a name for the fpp registers
|
||||||
|
|
||||||
ac0 = r0
|
ac0 = r0
|
||||||
|
|||||||
Reference in New Issue
Block a user