From 6280a4416e6ff2e862d97e7c98e219b0b6db4545 Mon Sep 17 00:00:00 2001 From: Olaf Seibert Date: Sat, 13 Mar 2021 16:49:16 +0100 Subject: [PATCH] Add test file with all opcodes. --- tests/RunTests | 1 + tests/test-opcodes.lst.ok | 300 ++++++++++++++++++++++++++++++++++++++ tests/test-opcodes.mac | 288 ++++++++++++++++++++++++++++++++++++ 3 files changed, 589 insertions(+) create mode 100644 tests/test-opcodes.lst.ok create mode 100644 tests/test-opcodes.mac diff --git a/tests/RunTests b/tests/RunTests index d97a13c..14afcda 100755 --- a/tests/RunTests +++ b/tests/RunTests @@ -24,6 +24,7 @@ TESTS="test-asciz \ test-locals \ test-macro-comma \ test-mcall-file \ + test-opcodes \ test-prec \ test-psect \ test-rad50 \ diff --git a/tests/test-opcodes.lst.ok b/tests/test-opcodes.lst.ok new file mode 100644 index 0000000..4d33ed0 --- /dev/null +++ b/tests/test-opcodes.lst.ok @@ -0,0 +1,300 @@ + 1 ;;;;; + 2 ; + 3 ; Use all opcodes once + 4 ; + 5 + 6 000000 000000 halt + 7 000002 000001 wait + 8 000004 000002 rti + 9 000006 000003 bpt + 10 000010 000004 iot + 11 000012 000005 reset + 12 000014 000006 rtt + 13 + 14 ; 00 00 07 ... 00 00 77 unused + 15 + 16 000016 000167 177774 jmp . + 17 000022 000207 rts pc + 18 + 19 ; 00 02 10 ... 00 02 27 unused + 20 + 21 000024 000233 spl 3 + 22 000026 000240 nop ; = clear NO condition codes + 23 + 24 000030 000241 clc + 25 000032 000242 clv + 26 000034 000244 clz + 27 000036 000250 cln + 28 000040 000257 ccc + 29 + 30 000042 000261 sec + 31 000044 000262 sev + 32 000046 000264 sez + 33 000050 000270 sen + 34 000052 000277 scc + 35 + 36 000054 000333 swab @(r3)+ + 37 + 38 000056 000777 br . + 39 000060 001377 bne . + 40 000062 001777 beq . + 41 000064 002377 bge . + 42 000066 002777 blt . + 43 000070 003377 bgt . + 44 000072 003777 ble . + 45 + 46 000074 004767 177774 jsr pc,. + 47 + 48 000100 005033 clr @(r3)+ + 49 000102 005133 com @(r3)+ + 50 000104 005233 inc @(r3)+ + 51 000106 005333 dec @(r3)+ + 52 000110 005433 neg @(r3)+ + 53 000112 005533 adc @(r3)+ + 54 000114 005633 sbc @(r3)+ + 55 000116 005733 tst @(r3)+ + 56 + 57 000120 006033 ror @(r3)+ + 58 000122 006133 rol @(r3)+ + 59 000124 006233 asr @(r3)+ + 60 000126 006333 asl @(r3)+ + 61 000130 006433 mark #33 + 62 000132 006533 mfpi @(r3)+ + 63 000134 006633 mtpi @(r3)+ + 64 000136 006733 sxt @(r3)+ + 65 + 66 ; 00 70 00 ... 00 77 77 unused + 67 + 68 000140 011122 mov (r1),(r2)+ + 69 000142 021122 cmp (r1),(r2)+ + 70 000144 031122 bit (r1),(r2)+ + 71 000146 041122 bic (r1),(r2)+ + 72 000150 051122 bis (r1),(r2)+ + 73 000152 061122 add (r1),(r2)+ + 74 + 75 000154 070211 mul (r1),r2 + 76 000156 071211 div (r1),r2 + 77 000160 072211 ash (r1),r2 + 78 000162 073211 ashc (r1),r2 + 79 000164 074122 xor r1,(r2)+ + 80 + 81 000166 075001 fadd r1 ; PDP-11/35, 11/40 floating point unit (FIS) + 82 000170 075011 fsub r1 + 83 000172 075021 fmul r1 + 84 000174 075031 fdiv r1 + 85 + 86 ; 07 50 40 ... 07 60 17 unused + 87 + 88 ; 07 60 20 ... 07 61 77 CIS Commercial Instruction Set + 89 + 90 ; 07600x unused + 91 ; 07601x unused + 92 000176 076020 l2d0 ; 07602x + 93 000200 076021 l2d1 + 94 000202 076022 l2d2 + 95 000204 076023 l2d3 + 96 000206 076024 l2d4 + 97 000210 076025 l2d5 + 98 000212 076026 l2d6 + 99 000214 076027 l2d7 + 100 + 101 000216 076030 movc ; 07603x + 102 000220 076031 movrc + 103 000222 076032 movtc + 104 ; 3..7? + 105 + 106 000224 076040 locc ;07604x + 107 000226 076041 skpc + 108 000230 076042 scanc + 109 000232 076043 spanc + 110 000234 076044 cmpc + 111 000236 076045 matc + 112 ; 6..7? + 113 + 114 000240 076050 addn ; 07605x + 115 000242 076051 subn + 116 000244 076052 cmpn + 117 000246 076053 cvtnl + 118 000250 076054 cvtpn + 119 000252 076055 cvtnp + 120 000254 076056 ashn + 121 000256 076057 cvtln + 122 + 123 000260 076060 l3d0 ; 07606x + 124 000262 076061 l3d1 + 125 000264 076062 l3d2 + 126 000266 076063 l3d3 + 127 000270 076064 l3d4 + 128 000272 076065 l3d5 + 129 000274 076066 l3d6 + 130 000276 076067 l3d7 + 131 + 132 000300 076070 addp ; 07607x + 133 000302 076071 subp + 134 000304 076072 cmpp + 135 000306 076073 cvtlp + 136 000310 076073 cvtpl + 137 000312 076074 mulp + 138 000314 076075 divp + 139 000316 076076 ashp + 140 ; 7? + 141 ; 07610x unused + 142 ; 07611x unused + 143 ; 07612x unused: would be L2D0I + 144 + 145 ; All the *I instructions need inline operands, which are omitted in this test. + 146 ; This Macro11 (as an extension) allows to specify them as arguments + 147 ; following the opcode, so you don't have to use inline .word directives. + 148 + 149 000320 076130 movci ; 07613x + 150 000322 076131 movrci + 151 000324 076132 movtci + 152 ; 3..7? + 153 + 154 000326 076140 locci ; 07614x + 155 000330 076141 skpci + 156 000332 076142 scanci + 157 000334 076143 spanci + 158 000336 076144 cmpci + 159 000340 076145 matci + 160 ; 6..7? + 161 + 162 000342 076150 addni ; 07615x + 163 000344 076151 subni + 164 000346 076152 cmpni + 165 000350 076153 cvtnli + 166 000352 076154 cvtpni + 167 000354 076155 cvtnpi + 168 000356 076156 ashni + 169 000360 076157 cvtlni + 170 + 171 ; 07616x unused: would be L3D0I + 172 + 173 000362 076170 addpi ; 07617x + 174 000364 076171 subpi + 175 000366 076172 cmppi + 176 000370 076177 cvtlpi + 177 000372 076173 cvtpli + 178 000374 076174 mulpi + 179 000376 076175 divpi + 180 000400 076176 ASHPI + 181 ; 7? + 182 + 183 ; 07 62 00 ... 07 67 77 unused + 184 + 185 000402 077101 sob r1,. + 186 + 187 000404 100377 bpl . + 188 000406 100777 bmi . + 189 000410 101377 bhi . + 190 000412 101777 blos . + 191 000414 102377 bvc . + 192 000416 103377 bcc . + 193 000420 103377 bhis . ; same + 194 000422 103777 bcs . + 195 000424 103777 blo . ; same + 196 + 197 000426 104000 emt #0 ; ... + 198 000430 104377 emt #255. + 199 000432 104400 trap #0 ; ... + 200 000434 104777 trap #255. + 201 + 202 000436 105033 clrb @(r3)+ + 203 000440 105133 comb @(r3)+ + 204 000442 105233 incb @(r3)+ + 205 000444 105333 decb @(r3)+ + 206 000446 105433 negb @(r3)+ + 207 000450 105533 adcb @(r3)+ + 208 000452 105633 sbcb @(r3)+ + 209 000454 105733 tstb @(r3)+ + 210 + 211 000456 106033 rorb @(r3)+ + 212 000460 106133 rolb @(r3)+ + 213 000462 106233 asrb @(r3)+ + 214 000464 106333 aslb @(r3)+ + 215 + 216 ; 10 64 00 ... 10 64 77 unused + 217 + 218 000466 106511 mfpd (r1) + 219 000470 106611 mtpd (r1) + 220 + 221 ; 10 67 00 ... 10 67 77 unused + 222 + 223 000472 111122 movb (r1),(r2)+ + 224 000474 121122 cmpb (r1),(r2)+ + 225 000476 131122 bitb (r1),(r2)+ + 226 000500 141122 bicb (r1),(r2)+ + 227 000502 151122 bisb (r1),(r2)+ + 228 000504 161122 sub (r1),(r2)+ + 229 + 230 ; 17 00 00 ... 17 77 77 Floating Point Processor (FPP) floating point + 231 + 232 000506 170000 cfcc + 233 000510 170001 setf + 234 000512 170002 seti + 235 000514 170011 setd + 236 000516 170012 setl + 237 + 238 000520 170131 ldfps @(r1)+ + 239 000522 170231 stfps @(r1)+ + 240 000524 170331 stst @(r1)+ + 241 + 242 000001 ac1 = %1 + 243 000005 ac5 = %5 + 244 + 245 000526 170405 clrf ac5 ; fdst: fpp register or general mode (not register) + 246 000530 170435 clrd @(r5)+ ; same opcode + 247 000532 170505 tstf ac5 + 248 000534 170535 tstd @(r5)+ ; same opcode + 249 000536 170605 absf ac5 + 250 000540 170635 absd @(r5)+ ; same opcode + 251 000542 170705 negf ac5 + 252 000544 170735 negd @(r5)+ ; same opcode + 253 + 254 000546 171135 mulf @(r5)+,ac1 + 255 000550 171105 muld ac5,ac1 ; same opcode + 256 000552 171535 modf @(r5)+,ac1 + 257 000554 171505 modd ac5,ac1 ; same opcode + 258 000556 172135 addf @(r5)+,ac1 + 259 000560 172105 addd r5,ac1 ; same opcode + 260 000562 172535 ldf @(r5)+,ac1 + 261 000564 172505 ldd r5,ac1 ; same opcode + 262 000566 173135 subf @(r5)+,ac1 + 263 000570 173105 subd r5,ac1 ; same opcode + 264 + 265 000572 173535 cmpf @(r5)+,ac1 + 266 000574 173505 cmpd r5,ac1 ; same opcode + 267 000576 174135 stf ac1,@(r5)+ + 268 000600 174105 std ac1,r5 ; same opcode + 269 000602 174535 divf @(r5)+,ac1 + 270 000604 174505 divd r5,ac1 ; same opcode + 271 + 272 000606 175135 stexp ac1,@(r5)+ + 273 000610 175535 stcfi ac1,@(r5)+ + 274 000612 175535 stcfl ac1,@(r5)+ ; same opcode + 275 000614 175535 stcdi ac1,@(r5)+ ; same opcode + 276 000616 175535 stcdl ac1,@(r5)+ ; same opcode + 277 000620 176135 stcfd ac1,@(r5)+ + 278 000622 176135 stcdf ac1,@(r5)+ ; same opcode + 279 + 280 000624 176535 ldexp @(r5)+,ac1 + 281 000626 177135 ldcif @(r5)+,ac1 ; same opcode + 282 000630 177135 ldcid @(r5)+,ac1 ; same opcode + 283 000632 177135 ldclf @(r5)+,ac1 ; same opcode + 284 000634 177135 ldcld @(r5)+,ac1 ; same opcode + 285 000636 177535 ldcdf @(r5)+,ac1 + 286 000640 177535 ldcfd @(r5)+,ac1 ; same opcode + 287 + 288 .end + 288 + + +Symbol table + +. ******R 001 AC1 =%000001 AC5 =%000005 + + +Program sections: + +. ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV) + 000642 001 (RW,I,LCL,REL,CON,NOSAV) diff --git a/tests/test-opcodes.mac b/tests/test-opcodes.mac new file mode 100644 index 0000000..58efa8a --- /dev/null +++ b/tests/test-opcodes.mac @@ -0,0 +1,288 @@ +;;;;; +; +; Use all opcodes once +; + + halt + wait + rti + bpt + iot + reset + rtt + + ; 00 00 07 ... 00 00 77 unused + + jmp . + rts pc + + ; 00 02 10 ... 00 02 27 unused + + spl 3 + nop ; = clear NO condition codes + + clc + clv + clz + cln + ccc + + sec + sev + sez + sen + scc + + swab @(r3)+ + + br . + bne . + beq . + bge . + blt . + bgt . + ble . + + jsr pc,. + + clr @(r3)+ + com @(r3)+ + inc @(r3)+ + dec @(r3)+ + neg @(r3)+ + adc @(r3)+ + sbc @(r3)+ + tst @(r3)+ + + ror @(r3)+ + rol @(r3)+ + asr @(r3)+ + asl @(r3)+ + mark #33 + mfpi @(r3)+ + mtpi @(r3)+ + sxt @(r3)+ + + ; 00 70 00 ... 00 77 77 unused + + mov (r1),(r2)+ + cmp (r1),(r2)+ + bit (r1),(r2)+ + bic (r1),(r2)+ + bis (r1),(r2)+ + add (r1),(r2)+ + + mul (r1),r2 + div (r1),r2 + ash (r1),r2 + ashc (r1),r2 + xor r1,(r2)+ + + fadd r1 ; PDP-11/35, 11/40 floating point unit (FIS) + fsub r1 + fmul r1 + fdiv r1 + + ; 07 50 40 ... 07 60 17 unused + + ; 07 60 20 ... 07 61 77 CIS Commercial Instruction Set + + ; 07600x unused + ; 07601x unused + l2d0 ; 07602x + l2d1 + l2d2 + l2d3 + l2d4 + l2d5 + l2d6 + l2d7 + + movc ; 07603x + movrc + movtc + ; 3..7? + + locc ;07604x + skpc + scanc + spanc + cmpc + matc + ; 6..7? + + addn ; 07605x + subn + cmpn + cvtnl + cvtpn + cvtnp + ashn + cvtln + + l3d0 ; 07606x + l3d1 + l3d2 + l3d3 + l3d4 + l3d5 + l3d6 + l3d7 + + addp ; 07607x + subp + cmpp + cvtlp + cvtpl + mulp + divp + ashp + ; 7? + ; 07610x unused + ; 07611x unused + ; 07612x unused: would be L2D0I + +; All the *I instructions need inline operands, which are omitted in this test. +; This Macro11 (as an extension) allows to specify them as arguments +; following the opcode, so you don't have to use inline .word directives. + + movci ; 07613x + movrci + movtci + ; 3..7? + + locci ; 07614x + skpci + scanci + spanci + cmpci + matci + ; 6..7? + + addni ; 07615x + subni + cmpni + cvtnli + cvtpni + cvtnpi + ashni + cvtlni + + ; 07616x unused: would be L3D0I + + addpi ; 07617x + subpi + cmppi + cvtlpi + cvtpli + mulpi + divpi + ASHPI + ; 7? + + ; 07 62 00 ... 07 67 77 unused + + sob r1,. + + bpl . + bmi . + bhi . + blos . + bvc . + bcc . + bhis . ; same + bcs . + blo . ; same + + emt #0 ; ... + emt #255. + trap #0 ; ... + trap #255. + + clrb @(r3)+ + comb @(r3)+ + incb @(r3)+ + decb @(r3)+ + negb @(r3)+ + adcb @(r3)+ + sbcb @(r3)+ + tstb @(r3)+ + + rorb @(r3)+ + rolb @(r3)+ + asrb @(r3)+ + aslb @(r3)+ + + ; 10 64 00 ... 10 64 77 unused + + mfpd (r1) + mtpd (r1) + + ; 10 67 00 ... 10 67 77 unused + + movb (r1),(r2)+ + cmpb (r1),(r2)+ + bitb (r1),(r2)+ + bicb (r1),(r2)+ + bisb (r1),(r2)+ + sub (r1),(r2)+ + + ; 17 00 00 ... 17 77 77 Floating Point Processor (FPP) floating point + + cfcc + setf + seti + setd + setl + + ldfps @(r1)+ + stfps @(r1)+ + stst @(r1)+ + +ac1 = %1 +ac5 = %5 + + clrf ac5 ; fdst: fpp register or general mode (not register) + clrd @(r5)+ ; same opcode + tstf ac5 + tstd @(r5)+ ; same opcode + absf ac5 + absd @(r5)+ ; same opcode + negf ac5 + negd @(r5)+ ; same opcode + + mulf @(r5)+,ac1 + muld ac5,ac1 ; same opcode + modf @(r5)+,ac1 + modd ac5,ac1 ; same opcode + addf @(r5)+,ac1 + addd r5,ac1 ; same opcode + ldf @(r5)+,ac1 + ldd r5,ac1 ; same opcode + subf @(r5)+,ac1 + subd r5,ac1 ; same opcode + + cmpf @(r5)+,ac1 + cmpd r5,ac1 ; same opcode + stf ac1,@(r5)+ + std ac1,r5 ; same opcode + divf @(r5)+,ac1 + divd r5,ac1 ; same opcode + + stexp ac1,@(r5)+ + stcfi ac1,@(r5)+ + stcfl ac1,@(r5)+ ; same opcode + stcdi ac1,@(r5)+ ; same opcode + stcdl ac1,@(r5)+ ; same opcode + stcfd ac1,@(r5)+ + stcdf ac1,@(r5)+ ; same opcode + + ldexp @(r5)+,ac1 + ldcif @(r5)+,ac1 ; same opcode + ldcid @(r5)+,ac1 ; same opcode + ldclf @(r5)+,ac1 ; same opcode + ldcld @(r5)+,ac1 ; same opcode + ldcdf @(r5)+,ac1 + ldcfd @(r5)+,ac1 ; same opcode + + .end