From 6369384e25bd26b19bbdac38e9a88a6526805820 Mon Sep 17 00:00:00 2001 From: Olaf Seibert Date: Sat, 13 Mar 2021 22:32:22 +0100 Subject: [PATCH] Add some missing instructions. - to tests: MFPT, MTPS, MFPS - also to opcode set: CSM, TSTSET, WRTLCK --- symbols.c | 3 + symbols.h | 14 +- tests/test-opcodes.lst.ok | 556 +++++++++++++++++++------------------- tests/test-opcodes.mac | 18 +- 4 files changed, 303 insertions(+), 288 deletions(-) diff --git a/symbols.c b/symbols.c index 26b8aa4..c564b96 100644 --- a/symbols.c +++ b/symbols.c @@ -413,6 +413,9 @@ void add_symbols( add_sym("XFC", I_XFC, OC_NONE, &instruction_section, &system_st); add_sym("XOR", I_XOR, OC_JSR, &instruction_section, &system_st); add_sym("MFPT", I_MFPT, OC_NONE, &instruction_section, &system_st); + add_sym("CSM", I_CSM, OC_1GEN, &instruction_section, &system_st); + add_sym("TSTSET", I_TSTSET, OC_1GEN, &instruction_section, &system_st); + add_sym("WRTLCK", I_WRTLCK, OC_1GEN, &instruction_section, &system_st); /* FPP instructions */ add_sym("ABSD", I_ABSD, OC_FPPDST, &instruction_section, &system_st); diff --git a/symbols.h b/symbols.h index 914a2ca..9b5e6d3 100644 --- a/symbols.h +++ b/symbols.h @@ -104,7 +104,8 @@ enum pseudo_ops { P_ASCII, P_IFDF }; -enum instruction_ops { I_ADC = 0005500, +enum instruction_ops { + I_ADC = 0005500, I_ADCB = 0105500, I_ADD = 0060000, I_ASH = 0072000, @@ -154,10 +155,10 @@ enum instruction_ops { I_ADC = 0005500, I_DECB = 0105300, I_DIV = 0071000, I_EMT = 0104000, - I_FADD = 0075000, - I_FDIV = 0075030, - I_FMUL = 0075020, - I_FSUB = 0075010, + I_FADD = 0075000, /* FIS */ + I_FDIV = 0075030, /* FIS */ + I_FMUL = 0075020, /* FIS */ + I_FSUB = 0075010, /* FIS */ I_HALT = 0000000, I_INC = 0005200, I_INCB = 0105200, @@ -207,6 +208,9 @@ enum instruction_ops { I_ADC = 0005500, I_XFC = 0076700, I_XOR = 0074000, I_MFPT = 0000007, + I_CSM = 0007000, + I_TSTSET = 0007200, + I_WRTLCK = 0007300, /* CIS - Commercial Instruction Set */ I_CIS_I = 0000100, /* Inline arguments */ I_CIS_P = 0000020, /* Packed instead of Numeric */ diff --git a/tests/test-opcodes.lst.ok b/tests/test-opcodes.lst.ok index 4d33ed0..43049c6 100644 --- a/tests/test-opcodes.lst.ok +++ b/tests/test-opcodes.lst.ok @@ -10,283 +10,287 @@ 10 000010 000004 iot 11 000012 000005 reset 12 000014 000006 rtt - 13 - 14 ; 00 00 07 ... 00 00 77 unused - 15 - 16 000016 000167 177774 jmp . - 17 000022 000207 rts pc - 18 - 19 ; 00 02 10 ... 00 02 27 unused - 20 - 21 000024 000233 spl 3 - 22 000026 000240 nop ; = clear NO condition codes - 23 - 24 000030 000241 clc - 25 000032 000242 clv - 26 000034 000244 clz - 27 000036 000250 cln - 28 000040 000257 ccc - 29 - 30 000042 000261 sec - 31 000044 000262 sev - 32 000046 000264 sez - 33 000050 000270 sen - 34 000052 000277 scc - 35 - 36 000054 000333 swab @(r3)+ - 37 - 38 000056 000777 br . - 39 000060 001377 bne . - 40 000062 001777 beq . - 41 000064 002377 bge . - 42 000066 002777 blt . - 43 000070 003377 bgt . - 44 000072 003777 ble . - 45 - 46 000074 004767 177774 jsr pc,. - 47 - 48 000100 005033 clr @(r3)+ - 49 000102 005133 com @(r3)+ - 50 000104 005233 inc @(r3)+ - 51 000106 005333 dec @(r3)+ - 52 000110 005433 neg @(r3)+ - 53 000112 005533 adc @(r3)+ - 54 000114 005633 sbc @(r3)+ - 55 000116 005733 tst @(r3)+ - 56 - 57 000120 006033 ror @(r3)+ - 58 000122 006133 rol @(r3)+ - 59 000124 006233 asr @(r3)+ - 60 000126 006333 asl @(r3)+ - 61 000130 006433 mark #33 - 62 000132 006533 mfpi @(r3)+ - 63 000134 006633 mtpi @(r3)+ - 64 000136 006733 sxt @(r3)+ - 65 - 66 ; 00 70 00 ... 00 77 77 unused - 67 - 68 000140 011122 mov (r1),(r2)+ - 69 000142 021122 cmp (r1),(r2)+ - 70 000144 031122 bit (r1),(r2)+ - 71 000146 041122 bic (r1),(r2)+ - 72 000150 051122 bis (r1),(r2)+ - 73 000152 061122 add (r1),(r2)+ - 74 - 75 000154 070211 mul (r1),r2 - 76 000156 071211 div (r1),r2 - 77 000160 072211 ash (r1),r2 - 78 000162 073211 ashc (r1),r2 - 79 000164 074122 xor r1,(r2)+ + 13 000016 000007 mfpt + 14 + 15 ; 00 00 10 ... 00 00 77 unused + 16 + 17 000020 000167 177774 jmp . + 18 000024 000207 rts pc + 19 + 20 ; 00 02 10 ... 00 02 27 unused + 21 + 22 000026 000233 spl 3 + 23 000030 000240 nop ; = clear NO condition codes + 24 + 25 000032 000241 clc + 26 000034 000242 clv + 27 000036 000244 clz + 28 000040 000250 cln + 29 000042 000257 ccc + 30 + 31 000044 000261 sec + 32 000046 000262 sev + 33 000050 000264 sez + 34 000052 000270 sen + 35 000054 000277 scc + 36 + 37 000056 000333 swab @(r3)+ + 38 + 39 000060 000777 br . + 40 000062 001377 bne . + 41 000064 001777 beq . + 42 000066 002377 bge . + 43 000070 002777 blt . + 44 000072 003377 bgt . + 45 000074 003777 ble . + 46 + 47 000076 004767 177774 jsr pc,. + 48 + 49 000102 005033 clr @(r3)+ + 50 000104 005133 com @(r3)+ + 51 000106 005233 inc @(r3)+ + 52 000110 005333 dec @(r3)+ + 53 000112 005433 neg @(r3)+ + 54 000114 005533 adc @(r3)+ + 55 000116 005633 sbc @(r3)+ + 56 000120 005733 tst @(r3)+ + 57 + 58 000122 006033 ror @(r3)+ + 59 000124 006133 rol @(r3)+ + 60 000126 006233 asr @(r3)+ + 61 000130 006333 asl @(r3)+ + 62 000132 006433 mark #33 + 63 000134 006533 mfpi @(r3)+ + 64 000136 006633 mtpi @(r3)+ + 65 000140 006733 sxt @(r3)+ + 66 + 67 000142 007033 csm @(r3)+ ; only some models + 68 ; 00 71 00 ... 00 71 77 unused + 69 000144 007233 tstset @(r3)+ ; only some models + 70 000146 007333 wrtlck @(r3)+ ; only some models + 71 + 72 ; 00 74 00 ... 00 77 77 unused + 73 + 74 000150 011122 mov (r1),(r2)+ + 75 000152 021122 cmp (r1),(r2)+ + 76 000154 031122 bit (r1),(r2)+ + 77 000156 041122 bic (r1),(r2)+ + 78 000160 051122 bis (r1),(r2)+ + 79 000162 061122 add (r1),(r2)+ 80 - 81 000166 075001 fadd r1 ; PDP-11/35, 11/40 floating point unit (FIS) - 82 000170 075011 fsub r1 - 83 000172 075021 fmul r1 - 84 000174 075031 fdiv r1 - 85 - 86 ; 07 50 40 ... 07 60 17 unused - 87 - 88 ; 07 60 20 ... 07 61 77 CIS Commercial Instruction Set - 89 - 90 ; 07600x unused - 91 ; 07601x unused - 92 000176 076020 l2d0 ; 07602x - 93 000200 076021 l2d1 - 94 000202 076022 l2d2 - 95 000204 076023 l2d3 - 96 000206 076024 l2d4 - 97 000210 076025 l2d5 - 98 000212 076026 l2d6 - 99 000214 076027 l2d7 - 100 - 101 000216 076030 movc ; 07603x - 102 000220 076031 movrc - 103 000222 076032 movtc - 104 ; 3..7? - 105 - 106 000224 076040 locc ;07604x - 107 000226 076041 skpc - 108 000230 076042 scanc - 109 000232 076043 spanc - 110 000234 076044 cmpc - 111 000236 076045 matc - 112 ; 6..7? - 113 - 114 000240 076050 addn ; 07605x - 115 000242 076051 subn - 116 000244 076052 cmpn - 117 000246 076053 cvtnl - 118 000250 076054 cvtpn - 119 000252 076055 cvtnp - 120 000254 076056 ashn - 121 000256 076057 cvtln - 122 - 123 000260 076060 l3d0 ; 07606x - 124 000262 076061 l3d1 - 125 000264 076062 l3d2 - 126 000266 076063 l3d3 - 127 000270 076064 l3d4 - 128 000272 076065 l3d5 - 129 000274 076066 l3d6 - 130 000276 076067 l3d7 - 131 - 132 000300 076070 addp ; 07607x - 133 000302 076071 subp - 134 000304 076072 cmpp - 135 000306 076073 cvtlp - 136 000310 076073 cvtpl - 137 000312 076074 mulp - 138 000314 076075 divp - 139 000316 076076 ashp - 140 ; 7? - 141 ; 07610x unused - 142 ; 07611x unused - 143 ; 07612x unused: would be L2D0I - 144 - 145 ; All the *I instructions need inline operands, which are omitted in this test. - 146 ; This Macro11 (as an extension) allows to specify them as arguments - 147 ; following the opcode, so you don't have to use inline .word directives. - 148 - 149 000320 076130 movci ; 07613x - 150 000322 076131 movrci - 151 000324 076132 movtci - 152 ; 3..7? - 153 - 154 000326 076140 locci ; 07614x - 155 000330 076141 skpci - 156 000332 076142 scanci - 157 000334 076143 spanci - 158 000336 076144 cmpci - 159 000340 076145 matci - 160 ; 6..7? - 161 - 162 000342 076150 addni ; 07615x - 163 000344 076151 subni - 164 000346 076152 cmpni - 165 000350 076153 cvtnli - 166 000352 076154 cvtpni - 167 000354 076155 cvtnpi - 168 000356 076156 ashni - 169 000360 076157 cvtlni - 170 - 171 ; 07616x unused: would be L3D0I - 172 - 173 000362 076170 addpi ; 07617x - 174 000364 076171 subpi - 175 000366 076172 cmppi - 176 000370 076177 cvtlpi - 177 000372 076173 cvtpli - 178 000374 076174 mulpi - 179 000376 076175 divpi - 180 000400 076176 ASHPI - 181 ; 7? - 182 - 183 ; 07 62 00 ... 07 67 77 unused - 184 - 185 000402 077101 sob r1,. - 186 - 187 000404 100377 bpl . - 188 000406 100777 bmi . - 189 000410 101377 bhi . - 190 000412 101777 blos . - 191 000414 102377 bvc . - 192 000416 103377 bcc . - 193 000420 103377 bhis . ; same - 194 000422 103777 bcs . - 195 000424 103777 blo . ; same - 196 - 197 000426 104000 emt #0 ; ... - 198 000430 104377 emt #255. - 199 000432 104400 trap #0 ; ... - 200 000434 104777 trap #255. - 201 - 202 000436 105033 clrb @(r3)+ - 203 000440 105133 comb @(r3)+ - 204 000442 105233 incb @(r3)+ - 205 000444 105333 decb @(r3)+ - 206 000446 105433 negb @(r3)+ - 207 000450 105533 adcb @(r3)+ - 208 000452 105633 sbcb @(r3)+ - 209 000454 105733 tstb @(r3)+ - 210 - 211 000456 106033 rorb @(r3)+ - 212 000460 106133 rolb @(r3)+ - 213 000462 106233 asrb @(r3)+ - 214 000464 106333 aslb @(r3)+ - 215 - 216 ; 10 64 00 ... 10 64 77 unused - 217 - 218 000466 106511 mfpd (r1) - 219 000470 106611 mtpd (r1) - 220 - 221 ; 10 67 00 ... 10 67 77 unused - 222 - 223 000472 111122 movb (r1),(r2)+ - 224 000474 121122 cmpb (r1),(r2)+ - 225 000476 131122 bitb (r1),(r2)+ - 226 000500 141122 bicb (r1),(r2)+ - 227 000502 151122 bisb (r1),(r2)+ - 228 000504 161122 sub (r1),(r2)+ - 229 - 230 ; 17 00 00 ... 17 77 77 Floating Point Processor (FPP) floating point - 231 - 232 000506 170000 cfcc - 233 000510 170001 setf - 234 000512 170002 seti - 235 000514 170011 setd - 236 000516 170012 setl - 237 - 238 000520 170131 ldfps @(r1)+ - 239 000522 170231 stfps @(r1)+ - 240 000524 170331 stst @(r1)+ + 81 000164 070211 mul (r1),r2 + 82 000166 071211 div (r1),r2 + 83 000170 072211 ash (r1),r2 + 84 000172 073211 ashc (r1),r2 + 85 000174 074122 xor r1,(r2)+ + 86 + 87 000176 075001 fadd r1 ; PDP-11/35, 11/40 floating point unit (FIS) + 88 000200 075011 fsub r1 + 89 000202 075021 fmul r1 + 90 000204 075031 fdiv r1 + 91 + 92 ; 07 50 40 ... 07 60 17 unused + 93 + 94 ; 07 60 20 ... 07 61 77 CIS Commercial Instruction Set + 95 + 96 ; 07600x unused + 97 ; 07601x unused + 98 000206 076020 l2d0 ; 07602x + 99 000210 076021 l2d1 + 100 000212 076022 l2d2 + 101 000214 076023 l2d3 + 102 000216 076024 l2d4 + 103 000220 076025 l2d5 + 104 000222 076026 l2d6 + 105 000224 076027 l2d7 + 106 + 107 000226 076030 movc ; 07603x + 108 000230 076031 movrc + 109 000232 076032 movtc + 110 ; 3..7? + 111 + 112 000234 076040 locc ;07604x + 113 000236 076041 skpc + 114 000240 076042 scanc + 115 000242 076043 spanc + 116 000244 076044 cmpc + 117 000246 076045 matc + 118 ; 6..7? + 119 + 120 000250 076050 addn ; 07605x + 121 000252 076051 subn + 122 000254 076052 cmpn + 123 000256 076053 cvtnl + 124 000260 076054 cvtpn + 125 000262 076055 cvtnp + 126 000264 076056 ashn + 127 000266 076057 cvtln + 128 + 129 000270 076060 l3d0 ; 07606x + 130 000272 076061 l3d1 + 131 000274 076062 l3d2 + 132 000276 076063 l3d3 + 133 000300 076064 l3d4 + 134 000302 076065 l3d5 + 135 000304 076066 l3d6 + 136 000306 076067 l3d7 + 137 + 138 000310 076070 addp ; 07607x + 139 000312 076071 subp + 140 000314 076072 cmpp + 141 000316 076073 cvtlp + 142 000320 076073 cvtpl + 143 000322 076074 mulp + 144 000324 076075 divp + 145 000326 076076 ashp + 146 ; 7? + 147 ; 07610x unused + 148 ; 07611x unused + 149 ; 07612x unused: would be L2D0I + 150 + 151 ; All the *I instructions need inline operands, which are omitted in this test. + 152 ; This Macro11 (as an extension) allows to specify them as arguments + 153 ; following the opcode, so you don't have to use inline .word directives. + 154 + 155 000330 076130 movci ; 07613x + 156 000332 076131 movrci + 157 000334 076132 movtci + 158 ; 3..7? + 159 + 160 000336 076140 locci ; 07614x + 161 000340 076141 skpci + 162 000342 076142 scanci + 163 000344 076143 spanci + 164 000346 076144 cmpci + 165 000350 076145 matci + 166 ; 6..7? + 167 + 168 000352 076150 addni ; 07615x + 169 000354 076151 subni + 170 000356 076152 cmpni + 171 000360 076153 cvtnli + 172 000362 076154 cvtpni + 173 000364 076155 cvtnpi + 174 000366 076156 ashni + 175 000370 076157 cvtlni + 176 + 177 ; 07616x unused: would be L3D0I + 178 + 179 000372 076170 addpi ; 07617x + 180 000374 076171 subpi + 181 000376 076172 cmppi + 182 000400 076177 cvtlpi + 183 000402 076173 cvtpli + 184 000404 076174 mulpi + 185 000406 076175 divpi + 186 000410 076176 ashpi + 187 ; 7? + 188 + 189 ; 07 62 00 ... 07 67 77 unused + 190 + 191 000412 077101 sob r1,. + 192 + 193 000414 100377 bpl . + 194 000416 100777 bmi . + 195 000420 101377 bhi . + 196 000422 101777 blos . + 197 000424 102377 bvc . + 198 000426 103377 bcc . + 199 000430 103377 bhis . ; same + 200 000432 103777 bcs . + 201 000434 103777 blo . ; same + 202 + 203 000436 104000 emt #0 ; ... + 204 000440 104377 emt #255. + 205 000442 104400 trap #0 ; ... + 206 000444 104777 trap #255. + 207 + 208 000446 105033 clrb @(r3)+ + 209 000450 105133 comb @(r3)+ + 210 000452 105233 incb @(r3)+ + 211 000454 105333 decb @(r3)+ + 212 000456 105433 negb @(r3)+ + 213 000460 105533 adcb @(r3)+ + 214 000462 105633 sbcb @(r3)+ + 215 000464 105733 tstb @(r3)+ + 216 + 217 000466 106033 rorb @(r3)+ + 218 000470 106133 rolb @(r3)+ + 219 000472 106233 asrb @(r3)+ + 220 000474 106333 aslb @(r3)+ + 221 + 222 000476 106433 mtps @(r3)+ + 223 000500 106511 mfpd (r1) + 224 000502 106611 mtpd (r1) + 225 000504 106733 mfps @(r3)+ + 226 + 227 000506 111122 movb (r1),(r2)+ + 228 000510 121122 cmpb (r1),(r2)+ + 229 000512 131122 bitb (r1),(r2)+ + 230 000514 141122 bicb (r1),(r2)+ + 231 000516 151122 bisb (r1),(r2)+ + 232 000520 161122 sub (r1),(r2)+ + 233 + 234 ; 17 00 00 ... 17 77 77 Floating Point Processor (FPP) floating point + 235 + 236 000522 170000 cfcc + 237 000524 170001 setf + 238 000526 170002 seti + 239 000530 170011 setd + 240 000532 170012 setl 241 - 242 000001 ac1 = %1 - 243 000005 ac5 = %5 - 244 - 245 000526 170405 clrf ac5 ; fdst: fpp register or general mode (not register) - 246 000530 170435 clrd @(r5)+ ; same opcode - 247 000532 170505 tstf ac5 - 248 000534 170535 tstd @(r5)+ ; same opcode - 249 000536 170605 absf ac5 - 250 000540 170635 absd @(r5)+ ; same opcode - 251 000542 170705 negf ac5 - 252 000544 170735 negd @(r5)+ ; same opcode - 253 - 254 000546 171135 mulf @(r5)+,ac1 - 255 000550 171105 muld ac5,ac1 ; same opcode - 256 000552 171535 modf @(r5)+,ac1 - 257 000554 171505 modd ac5,ac1 ; same opcode - 258 000556 172135 addf @(r5)+,ac1 - 259 000560 172105 addd r5,ac1 ; same opcode - 260 000562 172535 ldf @(r5)+,ac1 - 261 000564 172505 ldd r5,ac1 ; same opcode - 262 000566 173135 subf @(r5)+,ac1 - 263 000570 173105 subd r5,ac1 ; same opcode - 264 - 265 000572 173535 cmpf @(r5)+,ac1 - 266 000574 173505 cmpd r5,ac1 ; same opcode - 267 000576 174135 stf ac1,@(r5)+ - 268 000600 174105 std ac1,r5 ; same opcode - 269 000602 174535 divf @(r5)+,ac1 - 270 000604 174505 divd r5,ac1 ; same opcode - 271 - 272 000606 175135 stexp ac1,@(r5)+ - 273 000610 175535 stcfi ac1,@(r5)+ - 274 000612 175535 stcfl ac1,@(r5)+ ; same opcode - 275 000614 175535 stcdi ac1,@(r5)+ ; same opcode - 276 000616 175535 stcdl ac1,@(r5)+ ; same opcode - 277 000620 176135 stcfd ac1,@(r5)+ - 278 000622 176135 stcdf ac1,@(r5)+ ; same opcode - 279 - 280 000624 176535 ldexp @(r5)+,ac1 - 281 000626 177135 ldcif @(r5)+,ac1 ; same opcode - 282 000630 177135 ldcid @(r5)+,ac1 ; same opcode - 283 000632 177135 ldclf @(r5)+,ac1 ; same opcode - 284 000634 177135 ldcld @(r5)+,ac1 ; same opcode - 285 000636 177535 ldcdf @(r5)+,ac1 - 286 000640 177535 ldcfd @(r5)+,ac1 ; same opcode - 287 - 288 .end - 288 + 242 000534 170131 ldfps @(r1)+ + 243 000536 170231 stfps @(r1)+ + 244 000540 170331 stst @(r1)+ + 245 + 246 000001 ac1 = %1 + 247 000005 ac5 = %5 + 248 + 249 000542 170405 clrf ac5 ; fdst: fpp register or general mode (not register) + 250 000544 170435 clrd @(r5)+ ; same opcode + 251 000546 170505 tstf ac5 + 252 000550 170535 tstd @(r5)+ ; same opcode + 253 000552 170605 absf ac5 + 254 000554 170635 absd @(r5)+ ; same opcode + 255 000556 170705 negf ac5 + 256 000560 170735 negd @(r5)+ ; same opcode + 257 + 258 000562 171135 mulf @(r5)+,ac1 + 259 000564 171105 muld ac5,ac1 ; same opcode + 260 000566 171535 modf @(r5)+,ac1 + 261 000570 171505 modd ac5,ac1 ; same opcode + 262 000572 172135 addf @(r5)+,ac1 + 263 000574 172105 addd r5,ac1 ; same opcode + 264 000576 172535 ldf @(r5)+,ac1 + 265 000600 172505 ldd r5,ac1 ; same opcode + 266 000602 173135 subf @(r5)+,ac1 + 267 000604 173105 subd r5,ac1 ; same opcode + 268 + 269 000606 173535 cmpf @(r5)+,ac1 + 270 000610 173505 cmpd r5,ac1 ; same opcode + 271 000612 174135 stf ac1,@(r5)+ + 272 000614 174105 std ac1,r5 ; same opcode + 273 000616 174535 divf @(r5)+,ac1 + 274 000620 174505 divd r5,ac1 ; same opcode + 275 + 276 000622 175135 stexp ac1,@(r5)+ + 277 000624 175535 stcfi ac1,@(r5)+ + 278 000626 175535 stcfl ac1,@(r5)+ ; same opcode + 279 000630 175535 stcdi ac1,@(r5)+ ; same opcode + 280 000632 175535 stcdl ac1,@(r5)+ ; same opcode + 281 000634 176135 stcfd ac1,@(r5)+ + 282 000636 176135 stcdf ac1,@(r5)+ ; same opcode + 283 + 284 000640 176535 ldexp @(r5)+,ac1 + 285 000642 177135 ldcif @(r5)+,ac1 ; same opcode + 286 000644 177135 ldcid @(r5)+,ac1 ; same opcode + 287 000646 177135 ldclf @(r5)+,ac1 ; same opcode + 288 000650 177135 ldcld @(r5)+,ac1 ; same opcode + 289 000652 177535 ldcdf @(r5)+,ac1 + 290 000654 177535 ldcfd @(r5)+,ac1 ; same opcode + 291 + 292 .end + 292 Symbol table @@ -297,4 +301,4 @@ Symbol table Program sections: . ABS. 000000 000 (RW,I,GBL,ABS,OVR,NOSAV) - 000642 001 (RW,I,LCL,REL,CON,NOSAV) + 000656 001 (RW,I,LCL,REL,CON,NOSAV) diff --git a/tests/test-opcodes.mac b/tests/test-opcodes.mac index 58efa8a..b4e9a32 100644 --- a/tests/test-opcodes.mac +++ b/tests/test-opcodes.mac @@ -10,8 +10,9 @@ iot reset rtt + mfpt - ; 00 00 07 ... 00 00 77 unused + ; 00 00 10 ... 00 00 77 unused jmp . rts pc @@ -63,7 +64,12 @@ mtpi @(r3)+ sxt @(r3)+ - ; 00 70 00 ... 00 77 77 unused + csm @(r3)+ ; only some models + ; 00 71 00 ... 00 71 77 unused + tstset @(r3)+ ; only some models + wrtlck @(r3)+ ; only some models + + ; 00 74 00 ... 00 77 77 unused mov (r1),(r2)+ cmp (r1),(r2)+ @@ -177,7 +183,7 @@ cvtpli mulpi divpi - ASHPI + ashpi ; 7? ; 07 62 00 ... 07 67 77 unused @@ -213,12 +219,10 @@ asrb @(r3)+ aslb @(r3)+ - ; 10 64 00 ... 10 64 77 unused - + mtps @(r3)+ mfpd (r1) mtpd (r1) - - ; 10 67 00 ... 10 67 77 unused + mfps @(r3)+ movb (r1),(r2)+ cmpb (r1),(r2)+