open-simh.simtools/tests/test-float.mac
Olaf Seibert 3eb7274625 Add some FP test cases, including some parse errors.
Adjust the parsing a bit, and generate 0 values for bad syntax
like the reference version does.
2022-06-19 16:16:31 +02:00

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;;;;;
;
; Test floating point numbers.
;
; The values in the comments are the reference values from MACRO V05.05.
;
.word ^F 1.0 ; 040200
.word ^F-1.0 ; 140200
.word -^F 1.0 ; 137600
.word -^F-1.0 ; 037600
.word ^F6.2 ; 040706
.word ^C^F6.2 ; 137071
.word ^C<^F6.2> ; 137071
.flt2 6.2 ; 040706 063146
.flt4 6.2 ; 040706 063146 063146 063146
.flt2 1.5 ; 040300 000000
.flt4 1.5 ; 040300 000000 000000 000000
.word ^F 3.1415926535897932384626433 ; 040511
.flt2 3.1415926535897932384626433 ; 040511 007733
.flt4 3.1415926535897932384626433 ; 040511 007732 121041 064302
; Test some large numbers at the edge of the exactly representable
; integers.
; 1 << 56 just barely fits: it uses 57 bits but the lsb is 0 so
; when it is cut off, we don't notice.
; 1 << 56 + 1 R the lsb are 01 and is cut off.
; 1 << 56 + 2 the lsb are 10 and the missing 0 goes unnoticed.
; 1 << 56 - 1 consists of 56 1 bits. This value and all smaller ints
; 1 << 56 - 2 get represented exactly.
; Going up, to rounding steps of 4:
;
; 1 << 57
; 1 << 57 + 4 next higher available representation
; 1 << 57 + 8 next higher available representation
; 1 << 56 - 3
.flt4 72057594037927933 ; 056177 177777 177777 177775
; 1 << 56 - 2
.flt4 72057594037927934 ; 056177 177777 177777 177776
; 1 << 56 - 1
.word ^F 72057594037927935 ; 056200 (rounded up!)
.flt2 72057594037927935 ; 056200 000000 (rounded up!)
.flt4 72057594037927935 ; 056177 177777 177777 177777
; 1 << 56
.word ^F 72057594037927936 ; 056200
.flt2 72057594037927936 ; 056200 000000
.flt4 72057594037927936 ; 056200 000000 000000 000000
.flt4 72057594037927938 ; 1 << 56 + 2
; 056200 000000 000000 000001
.flt4 144115188075855872 ; 1 << 57
; 056400 000000 000000 000000
.flt4 144115188075855873 ; 1 << 57 + 1
; 056400 000000 000000 000000 (inexact)
.flt4 144115188075855874 ; 1 << 57 + 2
; 056400 000000 000000 000001 (inexact)
.flt4 144115188075855875 ; 1 << 57 + 3
; 056400 000000 000000 000001 (inexact)
.flt4 144115188075855876 ; 1 << 57 + 4
; 056400 000000 000000 000001 (exact!)
.flt4 144115188075855880 ; 1 << 57 + 8
; 056400 000000 000000 000002 (exact!)
; This one triggers rounding up (round == 1)
.flt4 6.66666 ; 040725 052507 055061 122276
; MACRO-11 truncates these ^F values despite what the manual says.
; On the other hand, it does round up some of the test values above.
; We stick to the manual since the result is more consistent.
; Expression RT-11 this
; MACRO-11 version
; V05.06
.word ^F 0.994140625 ; (2**9-3)/2**9 040176 040177
.flt4 0.994140625 ; same-> 040176 100000 0 0
.word ^F 0.998046875 ; (2**9-1)/2**9 040177 040200
.flt4 0.998046875 ; same-> 040177 100000 0 0
.word ^F 1.00390625 ; (2**8+1)/2**8 040200 040201
.flt4 1.00390625 ; same-> 040200 100000 0 0
.word ^F 1.01171875 ; (2**8+3)/2**8 040201 040202
.flt4 1.01171875 ; same-> 040201 100000 0 0
.flt4 1.701411834604692307e+38 ; 077777 177777 177777 177777
.FLT4 170141183460469230551095682998472802304 ; 2**127-2**70
.FLT4 170141183460469230564930741053754966015 ; 2**127-(2**70-2**64+2**62+1)
.FLT4 170141183460469230564930741053754966016 ; 2**127-(2**70-2**64+2**62+2)
.flt4 1.0000000000000000138777878078144567552953958511353 ; 0040200 0000000 0000000 0000000
.flt4 1.0000000000000000416333634234433702658861875534058 ; 0040200 0000000 0000000 0000001
.flt4 0.99999999999999997918331828827831486705690622329712 ; 0040177 0177777 0177777 0177776
.flt4 0.99999999999999999306110609609277162235230207443237 ; 0040177 0177777 0177777 0177777
.flt4 100E-2 ; 040200 000000 000000 000000
.flt4 1.0E5 ; 044303 050000 000000 000000
.flt4 1.0E10 ; 050425 001371 000000 000000
.flt4 1.0E20 ; 060655 074353 142654 061000
.flt4 1.0E30 ; 071111 171311 146404 063517
.flt4 1.0E38 ; 077626 073231 050265 006611
.flt4 1.0E-5 ; 034047 142654 043433 043604
.flt4 1.0E-10 ; 027733 163376 147275 166726
.flt4 1.0E-20 ; 017474 162410 062222 010433
.flt4 1.0E-30 ; 007242 041137 173536 012374
.flt4 1.0E-38 ; 000531 143734 166523 143442
.flt4 3681129745421959167 ; 057514 054000 000000 000000
.flt4 3681129745421959168 ; 0x3316000000000000 057514 054000 000000 000000
.flt4 3681129745421959169 ; 057514 054000 000000 000000
.flt4 3681129745421959170 ; 057514 054000 000000 000000
.flt4 14757170078986272767 ; 060114 146000 000000 000000
.flt4 14757170078986272768 ; 0xCCCC000000000000 060114 146000 000000 000000
.flt4 14757170078986272769 ; 060114 146000 000000 000000
.flt4 14757170078986272780 ; 060114 146000 000000 000000
.flt4 3.1415926535897932384626433 ; 040511 007732 121041 064302
; Try some possibly incomplete numbers
.flt4 + ; bad
.flt4 +1 ; ok
.flt4 +E1 ; bad
.flt4 - ; bad
.flt4 -1 ; ok
.flt4 -1. ; ok
.flt4 -1.. ; bad
.flt4 -E1 ; bad
.flt4 +. ; bad
.flt4 -. ; bad
.flt4 . ; bad
.flt4 .. ; bad
.flt4 .E10 ; bad
; Several ways to define a name for the fpp registers
ac0 = r0
ac1 = %1
f2 = %2
mulf r3,ac0
mulf r2,ac1
ADDF #^O41040,F2
addf #1,ac1
mulf r3,ac0
mulf r2,ac1
addf #^O41040,F2 ; taken literally
addf #1,ac1 ; as float
addf #1.,ac1 ; as float
addf #1.0,ac1 ; as float
addf #^D1,ac1 ; literally
subf #<1>,ac0 ; literally
addf #<1+1>,ac1 ; literally
subf #<1.0>,ac0 ; error
addf #1.5,ac1 ; as float
addd #-1.4,ac1 ; as float
subf #<^F 1.0>,ac0 ; as float
subf #<^D 1.0>,ac0 ; error
subf #<^D 1>,ac0 ; literally
subf #^D<1+1>,ac0 ; literally
subf #^D 1+1 ,ac0 ; literally
subf #1e3,ac0 ; as float
subf #1e 3,ac0 ; accepted by MACRO11 as 1E3 (but not 1 e3, 1 e 3)
a = 1
e3 = 3
subf #a,ac0 ; a interpreted as bit pattern
subf #<a>,ac0 ; a interpreted as bit pattern
subf #e3,ac0 ; e3 is the label
subf #<1e3>,ac0 ; error N
absf #2.5 ; bad: operand is destination
tstd #2.5 ; bad: operand is considered FDST by the arch handbook
stf ac0,#2.5 ; bad: junk at end of line
stf ac0,#2 ; doesn't makes sense but MACRO11 allows it
; Test immediate source argument for instructions that have one (src or fsrc)
addd #1,ac0 ; float
addf #1,ac0 ; float
cmpd #1,ac0 ; float
cmpf #1,ac0 ; float
divd #1,ac0 ; float
divf #1,ac0 ; float
ldcdf #1,ac0 ; float
ldcfd #1,ac0 ; float
ldcid #1,ac0 ; integer
ldcif #1,ac0 ; integer
ldcld #1,ac0 ; integer
ldclf #1,ac0 ; integer
ldd #1,ac0 ; float
ldf #1,ac0 ; float
ldexp #1,ac0 ; integer
modd #1,ac0 ; float
modf #1,ac0 ; float
muld #1,ac0 ; float
mulf #1,ac0 ; float
subd #1,ac0 ; float
subf #1,ac0 ; float
.end