mirror of
https://github.com/open-simh/simtools.git
synced 2026-01-13 15:27:18 +00:00
293 lines
5.9 KiB
Plaintext
293 lines
5.9 KiB
Plaintext
;;;;;
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;
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; Use all opcodes once
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;
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halt
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wait
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rti
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bpt
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iot
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reset
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rtt
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mfpt
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; 00 00 10 ... 00 00 77 unused
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jmp .
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rts pc
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; 00 02 10 ... 00 02 27 unused
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spl 3
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nop ; = clear NO condition codes
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clc
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clv
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clz
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cln
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ccc
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sec
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sev
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sez
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sen
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scc
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swab @(r3)+
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br .
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bne .
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beq .
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bge .
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blt .
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bgt .
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ble .
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jsr pc,.
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clr @(r3)+
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com @(r3)+
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inc @(r3)+
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dec @(r3)+
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neg @(r3)+
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adc @(r3)+
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sbc @(r3)+
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tst @(r3)+
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ror @(r3)+
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rol @(r3)+
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asr @(r3)+
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asl @(r3)+
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mark #33
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mfpi @(r3)+
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mtpi @(r3)+
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sxt @(r3)+
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csm @(r3)+ ; only some models
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; 00 71 00 ... 00 71 77 unused
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tstset @(r3)+ ; only some models
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wrtlck @(r3)+ ; only some models
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; 00 74 00 ... 00 77 77 unused
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mov (r1),(r2)+
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cmp (r1),(r2)+
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bit (r1),(r2)+
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bic (r1),(r2)+
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bis (r1),(r2)+
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add (r1),(r2)+
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mul (r1),r2
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div (r1),r2
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ash (r1),r2
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ashc (r1),r2
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xor r1,(r2)+
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fadd r1 ; PDP-11/35, 11/40 floating point unit (FIS)
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fsub r1
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fmul r1
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fdiv r1
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; 07 50 40 ... 07 60 17 unused
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; 07 60 20 ... 07 61 77 CIS Commercial Instruction Set
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; 07600x unused
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; 07601x unused
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l2d0 ; 07602x
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l2d1
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l2d2
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l2d3
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l2d4
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l2d5
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l2d6
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l2d7
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movc ; 07603x
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movrc
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movtc
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; 3..7?
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locc ;07604x
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skpc
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scanc
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spanc
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cmpc
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matc
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; 6..7?
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addn ; 07605x
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subn
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cmpn
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cvtnl
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cvtpn
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cvtnp
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ashn
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cvtln
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l3d0 ; 07606x
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l3d1
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l3d2
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l3d3
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l3d4
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l3d5
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l3d6
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l3d7
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addp ; 07607x
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subp
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cmpp
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cvtlp
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cvtpl
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mulp
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divp
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ashp
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; 7?
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; 07610x unused
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; 07611x unused
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; 07612x unused: would be L2D0I
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; All the *I instructions need inline operands, which are omitted in this test.
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; This Macro11 (as an extension) allows to specify them as arguments
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; following the opcode, so you don't have to use inline .word directives.
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movci ; 07613x
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movrci
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movtci
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; 3..7?
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locci ; 07614x
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skpci
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scanci
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spanci
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cmpci
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matci
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; 6..7?
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addni ; 07615x
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subni
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cmpni
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cvtnli
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cvtpni
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cvtnpi
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ashni
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cvtlni
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; 07616x unused: would be L3D0I
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addpi ; 07617x
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subpi
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cmppi
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cvtlpi
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cvtpli
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mulpi
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divpi
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ashpi
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; 7?
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; 07 62 00 ... 07 67 77 unused
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sob r1,.
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bpl .
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bmi .
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bhi .
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blos .
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bvc .
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bcc .
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bhis . ; same
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bcs .
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blo . ; same
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emt #0 ; ...
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emt #255.
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trap #0 ; ...
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trap #255.
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clrb @(r3)+
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comb @(r3)+
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incb @(r3)+
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decb @(r3)+
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negb @(r3)+
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adcb @(r3)+
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sbcb @(r3)+
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tstb @(r3)+
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rorb @(r3)+
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rolb @(r3)+
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asrb @(r3)+
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aslb @(r3)+
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mtps @(r3)+
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mfpd (r1)
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mtpd (r1)
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mfps @(r3)+
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movb (r1),(r2)+
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cmpb (r1),(r2)+
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bitb (r1),(r2)+
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bicb (r1),(r2)+
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bisb (r1),(r2)+
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sub (r1),(r2)+
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; 17 00 00 ... 17 77 77 Floating Point Processor (FPP) floating point
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cfcc
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setf
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seti
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setd
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setl
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ldfps @(r1)+
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stfps @(r1)+
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stst @(r1)+
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ac1 = %1
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ac5 = %5
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clrf ac5 ; fdst: fpp register or general mode (not register)
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clrd @(r5)+ ; same opcode
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tstf ac5
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tstd @(r5)+ ; same opcode
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absf ac5
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absd @(r5)+ ; same opcode
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negf ac5
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negd @(r5)+ ; same opcode
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mulf @(r5)+,ac1
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muld ac5,ac1 ; same opcode
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modf @(r5)+,ac1
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modd ac5,ac1 ; same opcode
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addf @(r5)+,ac1
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addd r5,ac1 ; same opcode
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ldf @(r5)+,ac1
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ldd r5,ac1 ; same opcode
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subf @(r5)+,ac1
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subd r5,ac1 ; same opcode
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cmpf @(r5)+,ac1
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cmpd r5,ac1 ; same opcode
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stf ac1,@(r5)+
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std ac1,r5 ; same opcode
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divf @(r5)+,ac1
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divd r5,ac1 ; same opcode
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stexp ac1,@(r5)+
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stcfi ac1,@(r5)+
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stcfl ac1,@(r5)+ ; same opcode
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stcdi ac1,@(r5)+ ; same opcode
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stcdl ac1,@(r5)+ ; same opcode
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stcfd ac1,@(r5)+
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stcdf ac1,@(r5)+ ; same opcode
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ldexp @(r5)+,ac1
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ldcif @(r5)+,ac1 ; same opcode
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ldcid @(r5)+,ac1 ; same opcode
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ldclf @(r5)+,ac1 ; same opcode
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ldcld @(r5)+,ac1 ; same opcode
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ldcdf @(r5)+,ac1
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ldcfd @(r5)+,ac1 ; same opcode
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.end
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