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@ -1,2 +1,11 @@
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# a2-boot
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## kernel - simple boot code example
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Sets up a limited addressing scheme using ERAT-only translation mode. Configuration block allows
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thread enablement and some per-thread configuration for MSR, code/stack addresses, and print buffer.
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Provides system call support for basic info and print buffer access.
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*a2lib* includes C functions for using system calls.
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7
kernel/bin/asm
Executable file
7
kernel/bin/asm
Executable file
@ -0,0 +1,7 @@
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#!/usr/bin/bash
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arch="-ma2"
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opts="-mregnames -mrelocatable -be"
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as $arch $opts -alhnd $1.s -o $1.out > $1.lst
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57
kernel/lib/a2lib.c
Normal file
57
kernel/lib/a2lib.c
Normal file
@ -0,0 +1,57 @@
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// © IBM Corp. 2020
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// Licensed under and subject to the terms of the CC-BY 4.0
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// license (https://creativecommons.org/licenses/by/4.0/legalcode).
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// Additional rights, including the right to physically implement a softcore
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// that is compliant with the required sections of the Power ISA
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// Specification, will be available at no cost via the OpenPOWER Foundation.
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// This README will be updated with additional information when OpenPOWER's
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// license is available.
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// Functions for accessing a2 kernel syscalls
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// whoami() - get thread id
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// tick() - get timer tick
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// _putchar(c) - write char c to print buffer
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#include "a2lib.h"
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// sc 0x0001
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uint32_t whoami(void) {
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uint32_t thread;
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asm volatile(
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"li 3,0x0001\n"
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"sc\n"
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"mr %0,3\n"
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: "=r"(thread) // outputs
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: // inputs
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: "r0","r3" // clobbers
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);
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return thread;
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}
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// sc 0x0010
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uint64_t tick(void) {
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uint64_t t;
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asm volatile(
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"li 3,0x0010\n"
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"sc\n"
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"mr %0,3\n"
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: "=r"(t) // outputs
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: // inputs
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: "r0","r3" // clobbers
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);
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return t;
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}
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// sc 0x0100
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void _putchar(char c) {
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asm volatile(
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"mr 4,%0\n"
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"li 3,0x0100\n"
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"sc\n"
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: // outputs
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: "r"(c) // inputs
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: "r0","r3","r4","r5","r6","r7","r8" // clobbers
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);
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}
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15
kernel/lib/a2lib.h
Normal file
15
kernel/lib/a2lib.h
Normal file
@ -0,0 +1,15 @@
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// © IBM Corp. 2020
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// Licensed under and subject to the terms of the CC-BY 4.0
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// license (https://creativecommons.org/licenses/by/4.0/legalcode).
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// Additional rights, including the right to physically implement a softcore
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// that is compliant with the required sections of the Power ISA
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// Specification, will be available at no cost via the OpenPOWER Foundation.
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// This README will be updated with additional information when OpenPOWER's
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// license is available.
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#include "stdint.h"
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uint32_t whoami(void);
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uint64_t tick(void);
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void _putchar(char c);
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601
kernel/src/boot.s
Normal file
601
kernel/src/boot.s
Normal file
@ -0,0 +1,601 @@
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# © IBM Corp. 2020
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# Licensed under and subject to the terms of the CC-BY 4.0
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# license (https://creativecommons.org/licenses/by/4.0/legalcode).
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# Additional rights, including the right to physically implement a softcore
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# that is compliant with the required sections of the Power ISA
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# Specification, will be available at no cost via the OpenPOWER Foundation.
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# This README will be updated with additional information when OpenPOWER's
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# license is available.
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# boot kernel
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# set up translations
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# set up timer facilities
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# set up threads
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# call user code
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# process user rc
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# todo:
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# 1. skip_printf_init flag should be threaded
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.include "defines.s"
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.section .hwinit # @00000000
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int_000:
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b boot_start
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# critical input
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.align 5
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int_020:
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b .
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# debug
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.align 5
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int_040:
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b .
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# dsi
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.align 5
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int_060:
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b .
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# isi
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.align 5
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int_080:
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b .
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# external
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.align 5
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int_0A0:
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b .
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# alignment
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.align 5
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int_0C0:
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b .
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# program
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.align 5
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int_0E0:
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b .
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# fp unavailable
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.align 5
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int_100:
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b .
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# sc
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.align 5
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int_120:
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b int_120_handler
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# apu unavailable
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.align 5
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int_140:
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b .
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# decrementer
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.align 5
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int_160:
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b .
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# fit
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.align 5
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int_180:
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b .
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# watchdog
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.align 5
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int_1A0:
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b .
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# dtlb
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.align 5
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int_1C0:
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b .
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# itlb
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.align 5
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int_1E0:
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b .
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# vector unavailable
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.align 5
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int_200:
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b .
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#
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.align 5
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int_220:
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b .
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#
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.align 5
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int_240:
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b .
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#
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.align 5
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int_260:
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b .
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# doorbell
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.align 5
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int_280:
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b .
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# doorbell critical
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.align 5
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int_2A0:
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b .
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# doorbell guest
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.align 5
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int_2C0:
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b .
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# doorbell guest critical
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.align 5
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int_2E0:
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b .
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# hvsc
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.align 8
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int_300:
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b int_300_handler
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# hvpriv
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.align 5
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int_320:
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b .
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# lrat
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.align 5
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int_340:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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# initial translation
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# both erats:
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# 00000000 1M: (boot)
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# 10000000 1M: (test)
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.align 8
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boot_start:
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mfspr r5,tir # who am i?
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cmpdi r5,0x00 # skip unless T0
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bne init_t123
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lis r3,0x8C00 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# derat 31 @00000000
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li r0,0x001F # entry #31
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li r2,0x0015 # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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lwz r10,CONFIG+S_ERATW2(r0) # load parms for erat settings
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# derat 30 @100000000
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li r0,0x001E # entry #30
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lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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oris r8,r8,0x1000
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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lis r3,0x8800 # 32=ecl 36:37=tlbsel (10=i, 11=d)
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# ierat 15 @00000000
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li r0,0x000F # entry #15
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li r2,0x003F # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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li r4,0 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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mtspr mmucr0,r3
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eratwe r2,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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# *** leave the init'd entry 14 for MT access to FFFFFFC0
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# ierat 13 @10000000
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li r0,0x000D # entry #13
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lis r4,0x1000 # word 1 rpn(32:51)=32:51 rpn(22:31)=54:63
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li r8,0x025F # word 0 epn=32:51 class=52:53 v=54 x=55 size=56:59 thrd=60:63 size: 0001=4K 0011=64K 0101=1M 0111=16M 1010=1G
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oris r8,r8,0x1000
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eratwe r10,r0,2
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eratwe r4,r0,1
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eratwe r8,r0,0
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isync
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# ------------------------------------------------------------------------------------------------------------------------------
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# init
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#
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# T0-only
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# set up any core facilities, then enable the others if config'd
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init_t0:
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# switch to 64b
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lwz r10,CONFIG+S_MSR(r0)
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mtmsr r10
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isync
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# other init
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lis r1,0x0300 # icm=gicm=1
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mtspr epcr,r1
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# set up timer facs
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li r1,0 # clear
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mtspr dec,r1
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mtspr tbh,r1
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mtspr tbl,r1
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lis r2,0xFE00 # mask: clear enw,wis,wrs,dis,fis,udis
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mtspr tsr,r2
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mfspr r2,xucr0
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andi. r2,r2,0x0200 # set tcs=0
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mtspr xucr0,r2
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mtspr tsr,r1 # clear tsr
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mtspr tcr,r1 # disable all timers
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# set thread configuration
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lwz r1,CONFIG+S_FLAGS(r0)
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andi. r1,r1,0xF
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mtspr tens,r1 # 60:63 = tid 3:0 enabled
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#not r1,r1
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#mtspr tenc,r1 # in case T0 is marked disabled
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isync
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b boot_complete
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# except T0
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# just worry about myself
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init_t123:
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# switch to 64b
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lwz r10,CONFIG+S_MSR(r0)
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mtmsr r10
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isync
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b boot_complete
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# ------------------------------------------------------------------------------------------------------------------------------
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boot_complete:
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# set up thread and hop to it
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lwz r1,CONFIG+S_FLAGS(r0)
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andis. r1,r1,0x8000 # 1=skip initial printf init
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bne boot_complete_1
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bl printf_reset # wipe buffer
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boot_complete_1:
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lwz r1,CONFIG+S_FLAGS(r0)
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lis r2,0x7FFF # clear printf flag
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ori r2,r2,0xFFFF
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and r1,r1,r2
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stw r1,CONFIG+S_FLAGS(r0)
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mfspr r5,tir # who am i?
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sldi r5,r5,6 # 64B offset
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addi r5,r5,CONFIG+T_CONFIG
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lwz r11,T_MSR(r5)
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ld r12,T_STACK(r5)
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ld r13,T_ENTRY(r5)
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lwz r1,CONFIG+S_FLAGS(r0)
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andi. r1,r1,FLAG_EOT_SC
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beq eot_blr
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eot_sc:
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lwz r2,CONFIG+S_EOT_SC(r0)
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lis r1,0x4400 # 'sc 1'
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ori r1,r1,0022
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std r1,0x0(r2)
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mtlr r1 # prog will blr to sc
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b process_start
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eot_blr:
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bl 4
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mflr r1
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addi r1,r1,0x30 # !!!!!!!!!!!!!!! <-- WARNING!
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mtlr r1 # prog will blr to exec_complete
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process_start:
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mtspr srr1,r11 # msr
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mtspr srr0,r13 # @entry
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mr r1,r12 # @stack
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mfspr r3,tir # tid - main(tid) if yall want it
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mfspr r2,tb
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std r2,T_TIMER_START(r5)
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rfi
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nop # !!!!!!!!!!!!!!! pads for lr calc
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nop
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nop
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# ------------------------------------------------------------------------------------------------------------------------------
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exec_complete:
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# allow blr to here, or it will be entered by sc directly
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# user blr'd here...
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sc 1 # hvsc back to sup state
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exec_complete_sup:
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mfspr r5,tir # who am i?
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sldi r5,r5,6 # 64B offset
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addi r5,r5,CONFIG+T_CONFIG
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mfspr r2,tb
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std r2,T_TIMER_END(r5)
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cmpdi r3,0 # check rc
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beq pass
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b fail
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# ------------------------------------------------------------------------------------------------------------------------------
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# dead zone
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.align 8
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fail:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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||||
# happy ending
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.align 8
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pass:
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b .
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# ------------------------------------------------------------------------------------------------------------------------------
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||||
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||||
# dec
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.align 11
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int_800:
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b .
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# perf
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.align 5
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int_820:
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b .
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.set CONFIG,0x0A00
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# ------------------------------------------------------------------------------------------------------------------------------
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# config info
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.align 9
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.long 0x8002B000 # sup MSR cm=1 ce=1 ee=1 pr=0 fp=1 me=1 fe=00 de=0 is=0 ds=0
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.long 0x80000001 # flags: skip_printf_init=0 eot_sc=27 thr_en=28:31(T3:T0)
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.long 0x000000BF # erat w2 (test) # word 2 wlc=40:41 rsvd=42 u=44:47 r=48 c=49 wimge=52:56 vf=57 ux/sx=58:59 uw/sw=60:61 ur/sr=62:63
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.long 0x10000000 # @user eot sc
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# per-thread configs (64B each)
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.align 7
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.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
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||||
.long 0x00000000 #
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||||
.long 0x00000000 #
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||||
.long 0x1003FF00 # @stack
|
||||
.long 0x00000000 #
|
||||
.long 0x100004B0 # @entry
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||||
.long 0
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||||
.long 0x10030000 # @print_start
|
||||
.long 0
|
||||
.long 0x10031FFF # @print_end
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||||
.long 0
|
||||
.long 0x10030000 # print ptr
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||||
.quad 0 # start tb
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||||
.quad 0 # end tb
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||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 #
|
||||
.long 0x00000000 #
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||||
.long 0x1003DF00 # @stack
|
||||
.long 0x00000000 #
|
||||
.long 0x100004B0 # @entry
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||||
.long 0
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||||
.long 0x10032000 # @print_start
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||||
.long 0
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||||
.long 0x10033FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10032000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 # flags
|
||||
.long 0x00000000 #
|
||||
.long 0x1003BF00 # @stack
|
||||
.long 0x00000000 #
|
||||
.long 0x100004B0 # @entry
|
||||
.long 0
|
||||
.long 0x10034000 # @print_start
|
||||
.long 0
|
||||
.long 0x10035FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10034000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
.long 0x8002F000 # usr MSR cm=1 ce=1 ee=1 pr=1 fp=1 me=1 fe=00 de=0 is=0 ds=0
|
||||
.long 0x00000000 # flags
|
||||
.long 0x00000000 #
|
||||
.long 0x10039F00 # @stack
|
||||
.long 0x00000000 #
|
||||
.long 0x100004B0 # @entry
|
||||
.long 0
|
||||
.long 0x10036000 # @print_start
|
||||
.long 0
|
||||
.long 0x10037FFF # @print_end
|
||||
.long 0
|
||||
.long 0x10036000 # print ptr
|
||||
.quad 0 # start tb
|
||||
.quad 0 # end tb
|
||||
|
||||
|
||||
.set S_MSR,0x00
|
||||
.set S_FLAGS,0x04
|
||||
.set S_ERATW2,0x08
|
||||
.set S_EOT_SC,0x0C
|
||||
|
||||
.set T_CONFIG,0x80
|
||||
.set T_MSR,0x00
|
||||
.set T_FLAGS,0x04
|
||||
.set T_STACK,0x08
|
||||
.set T_ENTRY,0x10
|
||||
.set T_TIMER_START,0x30
|
||||
.set T_TIMER_END,0x38
|
||||
.set T_PRINTSTART, 0x18
|
||||
.set T_PRINTEND, 0x20
|
||||
.set T_PRINTF, 0x28
|
||||
.set FLAG_EOT_SC,0x10
|
||||
|
||||
|
||||
# ------------------------------------------------------------------------------------------------------------------------------
|
||||
# other stuff
|
||||
.align 10
|
||||
|
||||
# clear buffer and reset pointer to start
|
||||
.align 6
|
||||
printf_reset:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
addi r6,r5,T_PRINTSTART
|
||||
ld r7,0(r6) # buffer start
|
||||
addi r6,r5,T_PRINTEND
|
||||
ld r8,0(r6) # buffer end
|
||||
sub r8,r8,r7
|
||||
addi r8,r8,1 # num bytes
|
||||
|
||||
mtctr r8
|
||||
li r6,0
|
||||
mr r8,r7
|
||||
printf_reset_clr:
|
||||
stb r6,0(r8)
|
||||
addi r8,r8,1
|
||||
bdnz printf_reset_clr
|
||||
|
||||
addi r8,r5,T_PRINTF
|
||||
std r7,0(r8) # reset ptr
|
||||
|
||||
blr
|
||||
|
||||
|
||||
# hvsc
|
||||
.align 8
|
||||
# go to exec_complete_sup in sup mode
|
||||
int_300_handler:
|
||||
|
||||
lwz r0,CONFIG+S_MSR(r0)
|
||||
mtmsr r0
|
||||
isync
|
||||
b exec_complete_sup
|
||||
|
||||
# sc
|
||||
.align 8
|
||||
# r3 is id, remaining are function-specific
|
||||
# not preserving r0, r3-r9 right now
|
||||
#
|
||||
# 0001 whoami
|
||||
# 0010 tick
|
||||
# 0100 putchar r4=c
|
||||
# 0106 printf_mode *NI*
|
||||
# 0107 printf_rst
|
||||
#
|
||||
int_120_handler:
|
||||
|
||||
mflr r0
|
||||
|
||||
cmpdi r3,0x0001
|
||||
beq sc_whoami
|
||||
cmpdi r3,0x0010
|
||||
beq sc_tick
|
||||
cmpdi r3,0x100
|
||||
beq sc_putchar
|
||||
cmpdi r3,0x107
|
||||
beq sc_printf_rst
|
||||
|
||||
li r3,-1
|
||||
mtlr r0
|
||||
rfi
|
||||
|
||||
# thread id
|
||||
.align 6
|
||||
sc_whoami:
|
||||
mfspr r3,tir
|
||||
rfi
|
||||
|
||||
# tb
|
||||
.align 6
|
||||
sc_tick:
|
||||
mfspr r3,tb
|
||||
rfi
|
||||
|
||||
# wrap buffer; could add flag to stop when full, or reset
|
||||
.align 6
|
||||
sc_putchar:
|
||||
|
||||
mfspr r5,tir # who am i?
|
||||
sldi r5,r5,6 # 64B offset
|
||||
addi r5,r5,CONFIG+T_CONFIG
|
||||
|
||||
addi r6,r5,T_PRINTF
|
||||
ld r7,0(r6) # buffer ptr
|
||||
stb r4,0(r7) # store char
|
||||
addi r7,r7,1
|
||||
|
||||
addi r8,r5,T_PRINTEND
|
||||
ld r8,0(r8) # buffer end
|
||||
cmpd r7,r8
|
||||
li r3,0 # rc=normal
|
||||
ble sc_putchar_ok
|
||||
addi r8,r5,T_PRINTSTART
|
||||
ld r7,0(r8) # buffer start
|
||||
li r3,-1 # rc=full
|
||||
sc_putchar_ok:
|
||||
std r7,0(r6) # save ptr
|
||||
|
||||
rfi
|
||||
|
||||
# clear buffer and reset pointer to start
|
||||
.align 6
|
||||
sc_printf_rst:
|
||||
|
||||
mfctr r3
|
||||
|
||||
bl printf_reset
|
||||
|
||||
mtctr r3
|
||||
mtlr r0
|
||||
li r3,0
|
||||
|
||||
rfi
|
||||
|
||||
143
kernel/src/defines.s
Normal file
143
kernel/src/defines.s
Normal file
@ -0,0 +1,143 @@
|
||||
# © IBM Corp. 2020
|
||||
# Licensed under and subject to the terms of the CC-BY 4.0
|
||||
# license (https://creativecommons.org/licenses/by/4.0/legalcode).
|
||||
# Additional rights, including the right to physically implement a softcore
|
||||
# that is compliant with the required sections of the Power ISA
|
||||
# Specification, will be available at no cost via the OpenPOWER Foundation.
|
||||
# This README will be updated with additional information when OpenPOWER's
|
||||
# license is available.
|
||||
|
||||
#-----------------------------------------
|
||||
# Defines
|
||||
#-----------------------------------------
|
||||
|
||||
# Regs
|
||||
|
||||
.set r0, 0
|
||||
.set r1, 1
|
||||
.set r2, 2
|
||||
.set r3, 3
|
||||
.set r4, 4
|
||||
.set r5, 5
|
||||
.set r6, 6
|
||||
.set r7, 7
|
||||
.set r8, 8
|
||||
.set r9, 9
|
||||
.set r10,10
|
||||
.set r11,11
|
||||
.set r12,12
|
||||
.set r13,13
|
||||
.set r14,14
|
||||
.set r15,15
|
||||
.set r16,16
|
||||
.set r17,17
|
||||
.set r18,18
|
||||
.set r19,19
|
||||
.set r20,20
|
||||
.set r21,21
|
||||
.set r22,22
|
||||
.set r23,23
|
||||
.set r24,24
|
||||
.set r25,25
|
||||
.set r26,26
|
||||
.set r27,27
|
||||
.set r28,28
|
||||
.set r29,29
|
||||
.set r30,30
|
||||
.set r31,31
|
||||
|
||||
.set f0, 0
|
||||
.set f1, 1
|
||||
.set f2, 2
|
||||
.set f3, 3
|
||||
.set f4, 4
|
||||
.set f5, 5
|
||||
.set f6, 6
|
||||
.set f7, 7
|
||||
.set f8, 8
|
||||
.set f9, 9
|
||||
.set f10,10
|
||||
.set f11,11
|
||||
.set f12,12
|
||||
.set f13,13
|
||||
.set f14,14
|
||||
.set f15,15
|
||||
.set f16,16
|
||||
.set f17,17
|
||||
.set f18,18
|
||||
.set f19,19
|
||||
.set f20,20
|
||||
.set f21,21
|
||||
.set f22,22
|
||||
.set f23,23
|
||||
.set f24,24
|
||||
.set f25,25
|
||||
.set f26,26
|
||||
.set f27,27
|
||||
.set f28,28
|
||||
.set f29,29
|
||||
.set f30,30
|
||||
.set f31,31
|
||||
|
||||
.set cr0, 0
|
||||
.set cr1, 1
|
||||
.set cr2, 2
|
||||
.set cr3, 3
|
||||
.set cr4, 4
|
||||
.set cr5, 5
|
||||
.set cr6, 6
|
||||
.set cr7, 7
|
||||
|
||||
# SPR numbers
|
||||
|
||||
.set srr0, 26
|
||||
.set srr1, 27
|
||||
.set epcr, 307
|
||||
|
||||
.set dbsr, 304
|
||||
.set dbcr0, 308
|
||||
.set dbcr1, 309
|
||||
.set dbcr2, 310
|
||||
.set dbcr3, 848
|
||||
|
||||
.set ivpr, 63
|
||||
|
||||
.set iucr0, 1011
|
||||
.set iucr1, 883
|
||||
.set iucr2, 884
|
||||
|
||||
.set iudbg0, 888
|
||||
.set iudbg1, 889
|
||||
.set iudbg2, 890
|
||||
.set iulfsr, 891
|
||||
.set iullcr, 892
|
||||
|
||||
.set mmucr0, 1020
|
||||
.set mmucr1, 1021
|
||||
.set mmucr2, 1022
|
||||
.set mmucr3, 1023
|
||||
|
||||
.set tb, 268
|
||||
.set tbl, 284
|
||||
.set tbh, 285
|
||||
|
||||
.set dec, 22
|
||||
.set udec, 550
|
||||
.set tsr, 336
|
||||
.set tcr, 340
|
||||
|
||||
.set xucr0, 1014
|
||||
.set xucr1, 851
|
||||
.set xucr2, 1016
|
||||
.set xucr3, 852
|
||||
.set xucr4, 853
|
||||
|
||||
.set tens, 438
|
||||
.set tenc, 439
|
||||
.set tensr, 437
|
||||
|
||||
.set pid, 48
|
||||
.set pir, 286
|
||||
.set pvr, 287
|
||||
.set tir, 446
|
||||
|
||||
7
kernel/src/readme.md
Normal file
7
kernel/src/readme.md
Normal file
@ -0,0 +1,7 @@
|
||||
# A2 Boot Code
|
||||
|
||||
Assemble on a Power machine, or crosscompile.
|
||||
|
||||
```
|
||||
../bin/asm boot # assemble boot.s (boot.out, boot.lst)
|
||||
```
|
||||
Loading…
x
Reference in New Issue
Block a user