From 07b89edd3c7fc72949694571ae8635f31c3ce01d Mon Sep 17 00:00:00 2001 From: Lars Asplund Date: Sat, 13 Mar 2021 22:34:01 +0100 Subject: [PATCH] Setup CI. Currently there are no testbenches provided with the project but the CI will still verify that each push and pull request to the project can be compiled. If/when tests are added they will also be executed with each push and PR. --- .github/workflows/vunit_tests.yml | 13 +++++++++++++ README.md | 6 ++++-- 2 files changed, 17 insertions(+), 2 deletions(-) create mode 100644 .github/workflows/vunit_tests.yml diff --git a/.github/workflows/vunit_tests.yml b/.github/workflows/vunit_tests.yml new file mode 100644 index 0000000..3c79f5b --- /dev/null +++ b/.github/workflows/vunit_tests.yml @@ -0,0 +1,13 @@ +name: VUnit Tests +on: [push, pull_request] +jobs: + test: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v2 + - uses: srt32/git-actions@v0.0.3 + with: + args: git update-index --chmod=+x run.py + - uses: VUnit/vunit_action@master + with: + cmd: python3 ./run.py diff --git a/README.md b/README.md index 54799ad..cf82b46 100644 --- a/README.md +++ b/README.md @@ -1,3 +1,5 @@ +![](https://github.com/openpower-cores/a2i/workflows/VUnit%20Tests/badge.svg) + # A2I ## The Project @@ -8,7 +10,7 @@ See [Project Info](rel/readme.md) for details. ## The Core The [A2I core](rel/doc/A2_BGQ.pdf) was created as a high-frequency four-threaded design, optimized for throughput and targeted for 3+ GHz in 45nm technology. -It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection. +It is a 27 FO4 implementation, with an in-order pipeline supporting 1-4 threads. It fully supports Power ISA 2.06 using Book III-E. The core was also designed to support pluggable implementations of MMU and AXU logic macros. This includes elimination of the MMU and using ERAT-only mode for translation/protection. ## The History @@ -27,7 +29,7 @@ There may be uses for this core where a full feature-set is needed, and its limi The design of the A2L2 interface (core-to-L2/nest) is straightforward, and offers multiple configurable options for data interfacing. There is also some configurability for handling certain Power-specific features (core vs. L2). -The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc. +The ability to add an AXU that is tightly-coupled to the core enables many possibilities for special-purpose designs, like an open distributed Web 3.0 hardware/software system integrating streaming encryption, blockchain, semantic query, etc. ### Technology Scaling